Infineon TLE984 QX Series, Руководство пользователя

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User Manual 283 Rev. 1.1
2019-03-18
TLE984xQX
Microcontroller with LIN and Power Switches for Automotive Applications
Arm® Cortex®-M0 Core
Rotate Rotate right ROR Rd, Rn, Rs 1
Load Word LDR Rt, [Rn, <op2>] 2
1)
Halfword LDRH Rt, [Rn, <op2>] 2
1)
Byte LDRB Rt, [Rn, <op2>] 2
1)
Signed halfword LDRSH Rt, [Rn, <op2>] 2
1)
Signed byte LDRSB Rt, [Rn, <op2>] 2
1)
Register from PC relative address LDR Rt, label 2
1)
Multiple register, increment after LDM Rn, {<reglist>} 1 + N
Store Word STR Rt, [Rn, <op2>] 2
1)
Halfword STRH Rt, [Rn, <op2>] 2
1)
Byte STRB Rt, [Rn, <op2>] 2
1)
Multiple register, increment after STM Rn, {<reglist>} 1 + N
Push Push registers onto stack PUSH {<reglist>} 1 + N
Pop Pop registers from stack POP {<reglist>} 1 + N
Branch Conditional B <cc> <label> 1 or 1 + P
2)
Unconditional B <label> 1 + P
With link BL <label> 1 + P
Indirect BX Rm 1 + P
Indirect with link BLX Rm 1 + P
State change Supervisor call SVC #<imm> –
Disable interrupts CPSID i 1 or 2
Enable interrupts CPSIE i 1 or 2
Move to general register from special
register MRS Rd, <specreg> 1 or 2
Move to special regsiter from general
register MSR <specreg>, Rn 1 or 2
Breakpoint BKPT #<imm> –
Extend Signed halfword to word SXTH Rd, Rm 1
Signed byte to word SXTB Rd, Rm 1
Unsigned halfword UXTH Rd, Rm 1
Unsigned byte UXTB Rd, Rm 1
Bit field Clear BICS Rd, Rn, Rm 1
Reverse Bytes in word REV Rd, Rm 1
Bytes in both halfwords REV16 Rd, Rm 1
Signed bottom halfword REVSH Rd, Rm 1
Subtract RSBS Rd, Rn, #0 1
Table 157 Instruction Set Summary (cont’d)
Operation Description Mnemonic Cycles (without
wait states)