User Manual
98
Rev. 1.1
2019-03-18
TLE984xQX
Microcontroller with LIN and Power Switches for Automotive Applications
System Control Unit - Digital Modules (SCU-DM)
PDIV or NDIV, it must be waited for the PLL lock condition. This procedure is typically used for
increasing the VCO clock step-by-step.
7.3.3.7
Oscillator Watchdog Event or PLL Loss of Lock Detection
In case of detection of too low frequency of the external clock source
f
OSC
, the OSC-Too-Low flag
(OSC_CON.OSC2L) is set. If enabled by NMICON.NMIOWD, a trap request to the CPU is activated
correspondingly only in these two cases: 1) When PLL is in Prescaler Mode and OSCSS = 01 selecting
f
OSC
as PLL
input clock source and SYSCON0.SYSCLKSEL selects PLL clock output as the system frequency, or 2) When
SYSCON0.SYSCLKSEL selects
f
OSC
as the system frequency. With these 2 cases and the OSC2L condition, the
OWD NMI flag FNMIOWD in NMISR is set.
Note:
Do not restart the oscillator watchdog detection by setting bit OSC_CON.OSCWDTRST while PLL is in
Prescaler Mode, as the detection status (OSC_CON.OSC2L) takes some time to be stable.
An oscillator watchdog event normally leads to a following PLL loss-of-lock detection.
If PLL is not the system clock source (SYSCON0.SYSCLKSEL deselects PLL or PLL is in Prescaler Mode) when the
loss-of-lock is detected, only the lock flag is reset (PLL_CON.LOCK = 0). No loss-of-lock NMI is generated and
no further action is taken. Otherwise if PLL is selected as clock source for system frequency and VCOBYP = 0,
the PLL loss-of-lock NMI flag FNMIPLL in NMISR is set. If enabled by NMICON.NMIPLL, an NMI trap request to
the CPU is activated. In addition, the lock flag is reset. Note that in the first place, the LOCK flag has to be set
first before a loss-of-lock NMI request is generated. This avoids a potential PLL loss-of-lock NMI request after
device power-on reset.
On an oscillator watchdog event when PLL is in Prescaler Mode and external clock (OSC_HP) is selected as PLL
clock input; or on PLL loss-of-lock detection when PLL is in Normal Mode, the PLL will be switched to run in
the Freerunning Mode on the VCO base frequency divided by K2, which is enforced by hardware until the
Prescaler Mode is (re-)selected.
Due to the above, the PLL shall only run in Prescaler Mode when changing the PLL configuration or switching
between PLL operation modes.
7.3.3.8
Oscillator Watchdog Event or Loss of Lock Recovery
In case of oscillator watchdog NMI, user software can first check if the PLL remains locked. If not, the clock
system can be reconfigured again by executing the following sequence as the OWD NMI routine:
1. Restart the oscillator watchdog detection by setting bit OSC_CON.OSCWDTRST
2. Wait until OSC_CON.OSC2L is clear
3. When bit OSC_CON.OSC2L is cleared, then
a) The Prescaler Mode has to be selected (PLL_CON.VCOBYP = 1)
b) Setting the restart lock detection bit PLL_CON.RESLD = 1
c) Waiting until the PLL VCO part becomes locked (PLL_CON.LOCK = 1)
d) When the LOCK is set again, the Prescaler Mode can be deselected (PLL_CON.VCOBYP = 0) and normal
PLL operation is resumed.
4. Clear the OWD NMI flag FNMIOWD.
In the general case of PLL loss-of-lock or to re-configure the PLL settings, user software can try to configure
the clock system again by executing the following sequence:
1. If input clock source is from XTAL (
f
OSC
from OSC_HP), ensure the input frequency is above threshold by
checking OSC_CON.OSC2L.
2. The Prescaler Mode has to be selected (PLL_CON.VCOBYP = 1)
