User Manual
250
Rev. 1.1
2019-03-18
TLE984xQX
Microcontroller with LIN and Power Switches for Automotive Applications
Arm® Cortex®-M0 Core
9
Arm® Cortex®-M0 Core
9.1
Features
The key features of the Cortex®-M0 implemented are listed below.
Processor Core. A low gate count core, with low latency interrupt processing:
• Thumb
®
+ Thumb-2
®
Instruction Set
• Banked stack pointer (SP) only
• Handler and thread modes
• Thumb and debug states
• Interruptible-continued instructions LDM/STM, Push/Pop for low interrupt latency
• Automatic processor state saving and restoration for low latency Interrupt Service Routine (ISR) entry and
exit
• Arm® architecture v6-M Style
• ARMv6 unaligned accesses
• Systick (typ. 1ms)
Nested Vectored Interrupt Controller (NVIC) closely integrated with the processor core to achieve low
latency interrupt processing:
• External interrupts, configurable from 1 to 24
• 7 interrupt priority registers for levels from 0 up to 192 in steps of 64
• Dynamic repriorization of interrupts
• Priority grouping. This enables selection of pre-empting interrupt levels and non pre-empting interrupt
levels
• Support for tail-chaining and late arrival of interrupts. This enables back-to-back interrupt processing
without the overhead of state saving and restoration between interrupts.
• Processor state automatically saved on interrupt entry, and restored on interrupt exit, with no instruction
overhead
Bus interfaces
• Advanced High-performance Bus-Lite (AHB-Lite) interfaces