User Manual
668
Rev. 1.1
2019-03-18
TLE984xQX
Microcontroller with LIN and Power Switches for Automotive Applications
High-Speed Synchronous Serial Interface SSC1/SSC2
A
Phase Error
(Master or Slave Mode) is detected when the incoming data at pin MRST (Master Mode) or MTSR
(Slave Mode), sampled with the same frequency as the module clock, changes between one cycle before and
two cycles after the latching edge of the shift clock signal SCLK. This condition sets the error flag CON.PE and,
when enabled via CON.PEN, the error interrupt request line EIR.
Note:
When receiving and transmitting data in parallel, phase errors occur if the baud rate is configured
to f
hw_clk
/ 2.
A
Baud Rate Error
(Slave Mode) is detected when the incoming clock signal deviates from the programmed
baud rate by more than 100%, i.e. it is either more than double or less than half the expected baud rate. This
condition sets the error flag CON.BE and, when enabled via CON.BEN, the error interrupt request line EIR.
Using this error detection capability requires that the slave’s baud-rate generator is programmed to the same
baud rate as the master device. This feature detects false additional, or missing pulses on the clock line (within
a certain frame).
Note:
If this error condition occurs and bit CON.REN = 1, an automatic reset of the SSC will be performed in
case of this error. This is done to re-initialize the SSC if too few or too many clock pulses have been
detected.
Note:
This error can occur after any transfer if the communication is stopped. This is the case due to the
fact that the SSC module supports back-to-back transfers for multiple transfers. In order to handle
this, the baud rate detector expects after a finished transfer immediately a next clock cycle for a new
transfer.
A
Transmit Error
(Slave Mode) is detected when a transfer was initiated by the master (SS_CLK gets active)
but the transmit buffer TB of the slave was not updated since the last transfer. This condition sets the error
flag CON.TE and the error interrupt request line EIR, when enabled via CON.TEN. If a transfer starts while the
transmit buffer is not updated, the slave will shift out the ‘old’ contents of the shift register, which normally is
the data received during the last transfer. This may lead to corruption of the data on the transmit/receive line
in half-duplex mode (open drain configuration) if this slave is not selected for transmission. This mode
requires that slaves not selected for transmission only shift out ones; that is, their transmit buffers must be
loaded with ‘FFFF
H
’ prior to any transfer.
Note:
A slave with push/pull output drivers not selected for transmission, will normally have its output
drivers switched. However, in order to avoid possible conflicts or misinterpretations, it is
recommended to always load the slave's transmit buffer prior to any transfer.
The cause of an error interrupt request (receive, phase, baud rate, transmit error) can be identified by the error
status flags in control register CON.
Note:
In contrast to the error interrupt request line EIR, the error status flags CON.TE, CON.RE, CON.PE, and
CON.BE, are not reset automatically upon entry into the error interrupt service routine, but must be
cleared by software.
