NXP Semiconductors MPC5605BK, Reference Manual

Page: 133 / 964

Chapter 7 Clock Generation Module (MC_CGM)
MPC5606BK Microcontroller Reference Manual, Rev. 2
Freescale Semiconductor 133
• Contains a set of registers to control clock dividers for divided clock generation
• Supports multiple clock sources and maps their address spaces to its memory map
• Generates an output clock
• Guarantees glitchless clock transitions when changing the system clock selection
• Supports 8-, 16-, and 32-bit wide read/write accesses
7.3 Modes of operation
This section describes the basic functional modes of the MC_CGM.
7.3.1 Normal and reset modes of operation
During normal and reset modes of operation, the clock selection for the system clock is controlled by the
MC_ME.
7.4 External signal description
The MC_CGM delivers an output clock to the PA[0] pin for off-chip use and/or observation.
7.5 Memory map and register definition
NOTE
Any access to unused registers as well as write accesses to read-only
registers will:
• Not change register content
Table 7-1. MC_CGM register description
Address Name Description Size
Access
Location
Normal Supervisor Test
0xC3FE_0370 CGM_OC_EN Output Clock Enable word read read/write read/write on page 138
0xC3FE_0374 CGM_OCDS_SC Output Clock Division
Select byte read read/write read/write on page 138
0xC3FE_0378 CGM_SC_SS System Clock Select
Status byte read read read on page 139
0xC3FE_037C CGM_SC_DC0 System Clock Divider
Configuration 0 byte read read/write read/write on page 140
0xC3FE_037D CGM_SC_DC1 System Clock Divider
Configuration 1 byte read read/write read/write on page 140
0xC3FE_037E CGM_SC_DC2 System Clock Divider
Configuration 2 byte read read/write read/write on page 140
0xC3FE_0380 CGM_AC0_SC Aux Clock 0 Select
Control word read read/write read/write on page 141