NXP Semiconductors MPC5605BK, Reference Manual

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Chapter 2 Introduction
MPC5606BK Microcontroller Reference Manual, Rev. 2
38 Freescale Semiconductor
2.4.6 SRAM
The on-chip SRAM on the MPC5606BK features the following:
• As much as 80 KB general purpose SRAM
• Typical SRAM access time: 0 wait-state for reads and 32-bit writes; 1 wait-state for 8- and 16-bit
writes if back to back with a read to same memory block
• 32-bit ECC with single-bit correction, double-bit detection for data integrity
• Supports byte (8-bit), half word (16-bit), and word (32-bit) writes for optimal use of memory
• User transparent ECC encoding and decoding for byte, half word, and word accesses
• Separate internal power domain applied to 32 KB SRAM block or 8 KB SRAM block during
STANDBY modes to retain contents during low power mode
2.4.7 Memory Protection Unit (MPU)
The MPU provides the following features
• Eight region descriptors for per-master protection
• Start and end address defined with 32-byte granularity
• Overlapping regions supported
• Protection attributes can optionally include process ID
• Protection offered for Threeconcurrent read ports
• Read and write attributes for all masters
• Execute and supervisor/user mode attributes for processor masters
2.4.8 Boot Assist Module (BAM)
The device implements a Boot Assist Module (BAM):
• Block of read-only memory containing VLE code which is executed according to boot mode of the
device
• Download of code into internal SRAM possible via FlexCAN or LINFlex, afterwhich code can be
executed
Array_D Data Flash Block + 0x0000_0000
16 KB 16 KB
Data Flash Block + 0x0000_4000
16 KB 16 KB
Data Flash Block + 0x0000_8000
16 KB 16 KB
Data Flash Block + 0x0000_C000
16 KB 16 KB
Table 2-3. Flash memory partitioning (continued)
Array Address
MPC5605B MPC5606B
768 MB 1 MB