NXP Semiconductors MPC5605BK, Reference Manual

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Chapter 28 Analog-to-Digital Converter (ADC)
MPC5606BK Microcontroller Reference Manual, Rev. 2
762 Freescale Semiconductor
28.4.9.2 Power-down Exit Delay Register (PDEDR)
Address: Base + 0x00C4 Access: User read/write
0 1 2 3 4 5 6 7 8 9 10 11 12 13 14 15
R 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0
W
Reset 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0
16 17 18 19 20 21 22 23 24 25 26 27 28 29 30 31
R 0 0 0 0
DSD
W
Reset 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0
Figure 28-46. Decode Signals Delay Register (DSDR)
Table 28-37. DSDR field descriptions
Field Description
DSD Delay between the external decode signals and the start of the sampling phase
It is used to take into account the settling time of the external multiplexer.
The decode signal delay is calculated as: DSD × 1/frequency of ADC clock.
Note: When ADC clock = Peripheral Clock/2 the DSD has to be incremented by 2 to see an additional
ADC clock cycle delay on the decode signal.
For example:
DSD = 0; 0 ADC clock cycle delay
DSD = 2; 1 ADC clock cycle delay
DSD = 4; 2 ADC clock cycles delay
Address: Base + 0x00C8 Access: User read/write
0 1 2 3 4 5 6 7 8 9 10 11 12 13 14 15
R 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0
W
Reset 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0
16 17 18 19 20 21 22 23 24 25 26 27 28 29 30 31
R 0 0 0 0 0 0 0 0
PDED
W
Reset 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0
Figure 28-47. Power-down Exit Delay Register (PDEDR)