![NXP Semiconductors MPC5605BK Reference Manual Download Page 110](http://html.mh-extra.com/html/nxp-semiconductors/mpc5605bk/mpc5605bk_reference-manual_1721852110.webp)
Chapter 6 Clock Description
MPC5606BK Microcontroller Reference Manual, Rev. 2
110
Freescale Semiconductor
The SXOSC can be controlled via the SXOSC_CTL register. The OSCON bit controls the powerdown
while bit S_OSC provides the oscillator clock available status.
After system reset, the oscillator is put to powerdown state, and software has to switch on when required.
Whenever the SXOSC is switched on from off state, the OSCCNT counter starts. When it reaches the value
EOCV[7:0] × 512, the oscillator clock is made available to the system. Also, an interrupt pending
SXOSC_CTL[I_OSC] bit is set. An interrupt will be generated if the interrupt mask bit M_OSC is set.
The oscillator circuit can be bypassed by writing SXOSC_CTL[OSCBYP] bit to 1. This bit can only be
set by software. A system reset is needed to reset this bit. In this bypass mode, the output clock has the
same polarity as the external clock applied on the OSC32K_EXTAL pin and the oscillator status is forced
to 1. The bypass configuration is independent of the powerdown mode of the oscillator.
shows the truth table of different configurations of the oscillator.
The SXOSC clock can be further divided by a configurable factor in the range 1 to 32 to generate the
divided clock to match system requirements. This division factor is specified by SXOSC_CTL[OSCDIV]
field.
6.4.4
Register description
Table 6-4. SXOSC truth table
SXOSC_CTL fields
OSC32K_XTAL
OSC32K_EXTAL
SXOSC
Oscillator MODE
OSCON
OSCBYP
0
0
No crystal, High Z
No crystal, High Z
0
Powerdown, IDDQ
x
1
x
External clock
OSC32K_EXTAL
Bypass, OSC disabled
1
0
Crystal
Crystal
OSC32K_EXTAL
Normal, OSC enabled
Ground
External clock
OSC32K_EXTAL
Normal, OSC enabled
Address: 0xC3FE_0040
Access: Special read/write
0
1
2
3
4
5
6
7
8
9
10
11
12
13
14
15
R
OSCBYP
1
0
0
0
0
0
0
0
EOCV
W
RESET:
0
0
0
0
0
0
0
0
1
0
0
0
0
0
0
0
16
17
18
19
20
21
22
23
24
25
26
27
28
29
30
31
R
M_OSC
0
0
OSCDIV
I_OSC
2
0
0
0
0
0
S_OSC
OSCO
N
W
RESET:
0
0
0
0
0
0
0
0
0
0
0
0
0
0
0
0
Figure 6-3. Slow External Crystal Oscillator Control Register (SXOSC_CTL)
Summary of Contents for MPC5605BK
Page 2: ...This page is intentionally left blank...
Page 20: ...MPC5606BK Microcontroller Reference Manual Rev 2 20 Freescale Semiconductor...
Page 103: ...MPC5606BK Microcontroller Reference Manual Rev 2 Freescale Semiconductor 103 Clocks and power...
Page 645: ...MPC5606BK Microcontroller Reference Manual Rev 2 Freescale Semiconductor 643 Timers...
Page 715: ...MPC5606BK Microcontroller Reference Manual Rev 2 Freescale Semiconductor 713 ADC system...
Page 787: ...MPC5606BK Microcontroller Reference Manual Rev 2 Freescale Semiconductor 787 Memory...
Page 893: ...MPC5606BK Microcontroller Reference Manual Rev 2 Freescale Semiconductor 893 Integrity...
Page 943: ...MPC5606BK Microcontroller Reference Manual Rev 2 Freescale Semiconductor 943 Debug...