NXP Semiconductors MPC5605BK, Reference Manual

Page: 438 / 964

Chapter 23 LIN Controller (LINFlex)
MPC5606BK Microcontroller Reference Manual, Rev. 2
438 Freescale Semiconductor
23.7.1.6 UART mode status register (UARTSR)
RXEN Receiver Enable
0 Receiver disable.
1 Receiver enable.
This bit can be programmed only when the UART bit is set.
TXEN Transmitter Enable
0 Transmitter disable.
1 Transmitter enable.
This bit can be programmed only when the UART bit is set.
Note: Transmission starts when this bit is set and when writing DATA0 in the BDRL register.
OP Odd Parity
0 Sent parity is even.
1 Sent parity is odd.
This bit can be programmed in Initialization mode only when the UART bit is set.
PCE Parity Control Enable
0 Parity transmit/check disable.
1 Parity transmit/check enable.
This bit can be programmed in Initialization mode only when the UART bit is set.
WL Word Length in UART mode
0 7-bit data + parity bit.
1 8-bit data (or 9-bit if PCE is set).
This bit can be programmed in Initialization mode only when the UART bit is set.
UART UART mode enable
0 LIN mode.
1 UART mode.
This bit can be programmed in Initialization mode only.
Offset: 0x0014 Access: User read/write
0 1 2 3 4 5 6 7 8 9 10 11 12 13 14 15
R 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0
W
Reset 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0
16 17 18 19 20 21 22 23 24 25 26 27 28 29 30 31
R SZF OCF PE3 PE2 PE1 PE0 RMB FEF BOF RPS WUF 0 0 DRF DTF NF
W w1c w1c w1c w1c w1c w1c w1c w1c w1c w1c w1c w1c w1c w1c
Reset 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0
Figure 23-11. UART mode status register (UARTSR)
Table 23-10. UARTCR field descriptions (continued)
Field Description