NXP Semiconductors MPC5605BK, Reference Manual

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Chapter 34 Error Correction Status Module (ECSM)
MPC5606BK Microcontroller Reference Manual, Rev. 2
Freescale Semiconductor 925
programming model must match the size of the register, e.g., an n-bit register only supports n-bit writes,
etc. Attempted writes of a different size than the register width produce an error termination of the bus
cycle and no change to the targeted register.
34.4.2.1 Processor Core Type Register (PCT)
The PCT is a 16-bit read-only register specifying the architecture of the processor core in the device. The
state of this register is defined by a module input signal; it can only be read from the IPS programming
model. Any attempted write is ignored.
34.4.2.2 SoC-Defined Platform Revision Register (REV)
The REV is a 16-bit read-only register specifying a revision number. The state of this register is defined
by an input signal; it can only be read from the IPS programming model. Any attempted write is ignored.
34.4.2.3 IPS On-Platform Module Configuration Register (IOPMC)
The IOPMC is a 32-bit read-only register identifying the presence/absence of the 32 low-order IPS
peripheral modules connected to the primary IPI slave bus controller. The state of this register is defined
Offset: 0x00 Access: Read
0 1 2 3 4 5 6 7 8 9 10 11 12 13 14 15
R PCT
W
Reset 1 1 1 0 0 0 0 0 0 0 0 1 0 0 1 0
Figure 34-1. Processor Core Type Register (PCT)
Table 34-2. PCT field descriptions
Field Description
PCT Processor Core Type
Offset: 0x02 Access: Read
0 1 2 3 4 5 6 7 8 9 10 11 12 13 14 15
R REV
W
Reset 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0
Figure 34-2. SoC-Defined Platform Revision Register (REV)
Table 34-3. REV field descriptions
Field Description
REV Revision
The REV field is specified by an input signal to define a software-visible revision number.