NXP Semiconductors MPC5605BK, Reference Manual

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Chapter 25 FlexCAN
MPC5606BK Microcontroller Reference Manual, Rev. 2
Freescale Semiconductor 563
CLK_SRC CAN Engine Clock Source
This bit selects the clock source to the CAN Protocol Interface (CPI) to be either the peripheral clock
(driven by the PLL) or the crystal oscillator clock. The selected clock is the one fed to the prescaler to
generate the Serial Clock (Sclock). In order to guarantee reliable operation, this bit must only be
changed while the module is in Disable Mode. See
Section 25.5.9.4, Protocol timing , for more
information.
0 The CAN engine clock source is the oscillator clock
1 The CAN engine clock source is the bus clock
TWRN_MSK Tx Warning Interrupt Mask
This bit provides a mask for the Tx Warning Interrupt associated with the TWRN_INT flag in ESR.
This bit has no effect if the WRN_EN bit in MCR is negated and it is read as zero when WRN_EN is
negated.
0 Tx Warning Interrupt disabled
1 Tx Warning Interrupt enabled
RWRN_MSK Rx Warning Interrupt Mask
This bit provides a mask for the Rx Warning Interrupt associated with the RWRN_INT flag in ESR.
This bit has no effect if the WRN_EN bit in MCR is negated and it is read as zero when WRN_EN is
negated.
0 Rx Warning Interrupt disabled
1 Rx Warning Interrupt enabled
LPB Loop Back
This bit configures FlexCAN to operate in Loop-Back Mode. In this mode, FlexCAN performs an
internal loop back that can be used for self test operation. The bit stream output of the transmitter is
fed back internally to the receiver input. The Rx CAN input pin is ignored and the Tx CAN output goes
to the recessive state (logic 1). FlexCAN behaves as it normally does when transmitting, and treats
its own transmitted message as a message received from a remote node. In this mode, FlexCAN
ignores the bit sent during the ACK slot in the CAN frame acknowledge field, generating an internal
acknowledge bit to ensure proper reception of its own message. Both transmit and receive interrupts
are generated. This bit must be written in Freeze mode only.
0 Loop Back disabled
1 Loop Back enabled
SMP Sampling Mode
This bit defines the sampling mode of CAN bits at the Rx input. This bit must be written in Freeze
mode only.
0 Just one sample is used to determine the bit value
1 Three samples are used to determine the value of the received bit: the regular one (sample point)
and two preceding samples, a majority rule is used
BOFF_REC Bus Off Recovery Mode
This bit defines how FlexCAN recovers from Bus Off state. If this bit is negated, automatic recovering
from Bus Off state occurs according to the CAN Specification 2.0B. If the bit is asserted, automatic
recovering from Bus Off is disabled and the module remains in Bus Off state until the bit is negated
by the user. If the negation occurs before 128 sequences of 11 recessive bits are detected on the CAN
bus, then Bus Off recovery happens as if the BOFF_REC bit had never been asserted. If the negation
occurs after 128 sequences of 11 recessive bits occurred, then FlexCAN will resynchronize to the bus
by waiting for 11 recessive bits before joining the bus. After negation, the BOFF_REC bit can be
reasserted again during Bus Off, but it will only be effective the next time the module enters Bus Off.
If BOFF_REC was negated when the module entered Bus Off, asserting it during Bus Off will not be
effective for the current Bus Off recovery.
0 Automatic recovering from Bus Off state enabled, according to CAN Spec 2.0 part B
1 Automatic recovering from Bus Off state disabled
Table 25-10. CTRL field descriptions (continued)
Field Description