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NXP Semiconductors MPC5605BK, Reference Manual

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Chapter 3 Memory Map

MPC5606BK Microcontroller Reference Manual, Rev. 2

52

Freescale Semiconductor

 

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Summary of Contents for MPC5605BK

Page 1: ...MPC5606BK Microcontroller Reference Manual Devices Supported MPC5606BKRM Rev 2 05 2014 MPC5606BK MPC5605BK...

Page 2: ...This page is intentionally left blank...

Page 3: ...0h core processor 35 2 4 2 Crossbar switch XBAR 35 2 4 3 Interrupt Controller INTC 35 2 4 4 System Integration Unit Lite SIUL 36 2 4 5 Flash memory 36 2 4 6 SRAM 38 2 4 7 Memory Protection Unit MPU 38...

Page 4: ...map and register description 95 Chapter 6 Clock Description 6 1 Clock architecture 105 6 2 Clock gating 106 6 3 Fast external crystal oscillator FXOSC digital interface 107 6 3 1 Main features 107 6...

Page 5: ...of operation 133 7 4 External signal description 133 7 5 Memory map and register definition 133 7 5 1 Register descriptions 137 7 5 2 Output Clock Division Select Register CGM_OCDS_SC 138 7 5 3 Syste...

Page 6: ...193 Chapter 10 Power Control Unit MC_PCU 10 1 Introduction 195 10 1 1 Overview 195 10 1 2 Features 196 10 1 3 Modes of operation 196 10 2 External signal description 197 10 3 Memory map and register d...

Page 7: ...eup Interrupt Falling Edge Event Enable Register WIFEER 221 12 4 9 Wakeup Interrupt Filter Enable Register WIFER 221 12 4 10 Wakeup Interrupt Pullup Enable Register WIPUER 222 12 5 Functional descript...

Page 8: ...it features 249 15 4 4 e200z0h system bus features 249 15 5 Core registers and programmer s model 249 Chapter 16 Enhanced Direct Memory Access eDMA 16 1 Device specific features 253 16 2 Introduction...

Page 9: ...iagram 309 18 4 Modes of operation 309 18 4 1 Normal mode 309 18 5 Memory map and register description 311 18 5 1 Module memory map 311 18 5 2 Register description 311 18 6 Functional description 319...

Page 10: ...5 Memory map and register description 351 20 5 1 SIUL memory map 351 20 5 2 Register protection 352 20 5 3 Register descriptions 353 20 6 Functional description 372 20 6 1 Pad control 372 20 6 2 Gener...

Page 11: ...nterrupt Configuration Register IBIC 409 22 4 DMA Interface 409 22 5 Functional description 411 22 5 1 I Bus protocol 411 22 5 2 Interrupts 414 22 6 Initialization application information 415 22 6 1 I...

Page 12: ...de 476 24 7 3 Slave mode with identifier filtering 478 24 7 4 Slave mode with automatic resynchronization 481 24 8 Test modes 482 24 8 1 Loop Back mode 482 24 8 2 Self Test mode 483 24 9 UART mode 483...

Page 13: ...517 24 10 25 DMA Rx enable register DMARXE 518 24 11 DMA interface 518 24 11 1 Master node TX mode 519 24 11 2 Master node RX mode 522 24 11 3 Slave node TX mode 524 24 11 4 Slave node RX mode 527 24...

Page 14: ...nfigurations 592 Chapter 26 Deserial Serial Peripheral Interface DSPI 26 1 Introduction 593 26 2 Features 594 26 3 Modes of operation 595 26 3 1 Master mode 595 26 3 2 Slave mode 595 26 3 3 Module Dis...

Page 15: ...iew of the eMIOS 647 27 2 3 Overview of the PIT 649 27 3 System Timer Module STM 649 27 3 1 Introduction 649 27 3 2 External signal description 650 27 3 3 Memory map and register definition 650 27 3 4...

Page 16: ...28 4 3 Interrupt registers 740 28 4 4 DMA registers 748 28 4 5 Threshold registers 752 28 4 6 Presampling registers 753 28 4 7 Conversion timing registers CTR 0 2 756 28 4 8 Mask registers 757 28 4 9...

Page 17: ...880 30 8 3 Read cycles Buffer hit 881 30 8 4 Write cycles 881 30 8 5 Error termination 881 30 8 6 Access pipelining 881 30 8 7 Flash error response operation 882 30 8 8 Bank0 page read buffers and pre...

Page 18: ...915 33 6 Functional description 919 Chapter 34 Error Correction Status Module ECSM 34 1 Introduction 923 34 2 Overview 923 34 3 Features 923 34 4 Memory map and register description 923 34 4 1 Memory...

Page 19: ...3 TAP controller state machine 949 35 8 4 JTAGC instructions 951 35 8 5 Boundary scan 953 35 9 e200z0 OnCE controller 953 35 9 1 e200z0 OnCE controller block diagram 953 35 9 2 e200z0 OnCE controller...

Page 20: ...MPC5606BK Microcontroller Reference Manual Rev 2 20 Freescale Semiconductor...

Page 21: ...rogrammers who want to develop products with the MPC5606BK device It is assumed that the reader understands operating systems microprocessor system design basic principles of software and hardware and...

Page 22: ...o be configured including LVDs and provides status reporting 10 Power Control Unit MC_PCU Controls the power to different power domains within the microcontroller allowing SRAM to be selectively power...

Page 23: ...TC Provides the configuration and control of all of the external interrupts non core that are then routed to the IVOR4 core interrupt vector 19 Crossbar Switch XBAR Describes the connections of the XB...

Page 24: ...omatic reload 28 Analog to Digital Converter ADC Details the configuration and operation of the ADC modules as well as detailing the channels that are shared between the 10 bit and 12 bit ADC The ADC...

Page 25: ...ed in this section Registers can either be configured to be unlocked via a soft lock bit or locked unit the next reset Integrity 33 Software Watchdog Timer SWT The SWT offers a selection of configurab...

Page 26: ...K document set comprises This reference manual provides information on the features of the logical blocks on the device and how they are integrated with each other The device data sheet specifies the...

Page 27: ...se require configuration of the integration features of the microcontroller The module will normally have to be powered and enabled at system level then a clock may have to be explicitly chosen and fi...

Page 28: ...eet Certain pins have dedicated functions that affect the behavior of the MCU after reset These include pins to force test or alternate boot conditions and debug features These are described in Chapte...

Page 29: ...Each pin has a register PCR in the module that allows selection of the output functions that is connected to the pin The available settings for the PCR are described in Section 4 2 Pin muxing Inputs...

Page 30: ...ion software In general the software will configure an MC_ME mode to make certain peripherals clocks and memory active and then switch to that mode Chapter 6 Clock Description includes a graphic of th...

Page 31: ...edded category and only implements the VLE variable length encoding APU providing improved code density It operates at speeds as high as 64 MHz and offers high performance processing optimized for low...

Page 32: ...table shows example 2 Based on 125 C ambient operating temperature 3 Not shared with 12 bit ADC but possibly shared with other alternate functions 4 Not shared with 10 bit ADC but possibly shared with...

Page 33: ...ea Network CFlash Code flash memory CMU Clock Monitor Unit CTU Cross Triggering Unit DFlash Data flash memory DSPI Deserial Serial Peripheral Interface eDMA Enhanced Direct Memory Access eMIOS Enhance...

Page 34: ...al interface on the different pins of the device Inter integrated circuit I2 C bus A two wire bidirectional serial bus that provides a simple and efficient method of data exchange between devices Inte...

Page 35: ...eparate instruction bus and load store bus Harvard architecture Hardware vectored interrupt support Multi cycle divide word divw and load multiple word lmw store multiple word smw multiple class instr...

Page 36: ...rt alternative configuration as general purpose inputs with selected pins able to also support outputs Direct readback of the pin value supported on all digital output pins through the SIUL Configurab...

Page 37: ...CSM address space but data comes from the flash memory module Flash memory module can be interrogated to provide ECC bit error location Margin read for flash memory array supported for initial program...

Page 38: ...ry Protection Unit MPU The MPU provides the following features Eight region descriptors for per master protection Start and end address defined with 32 byte granularity Overlapping regions supported P...

Page 39: ...DMA transfer support available Table 2 4 shows the supported eMIOS modes Table 2 5 shows the maximum eMIOS channel allocation Table 2 4 Supported eMIOS channel modes Mode Channel type Description Nam...

Page 40: ...ching FIFOs for buffering as many as four transfers on the transmit and receive side General purpose I O functionality on pins when not used for SPI Queueing operation possible through use of eDMA 32...

Page 41: ...id PLL jitter Listen only mode capabilities CAN sampler available for connection to one of available CAN module pads Supports capturing of first message identifier while in STOP or STANDBY modes 2 4 1...

Page 42: ...stem timers include Peripheral Interrupt Timer PIT timers including ADC trigger One Real Time Counter RTC timer The PIT is an array of timers that can be used to raise interrupts trigger CTU channels...

Page 43: ...e enabled hard lock prevents any changes until after a reset Supports halting during low power modes 2 4 15 Inter Integrated Circuit I2 C module The I2 C module features the following One I2 C module...

Page 44: ...nels shared between 10 bit and 12 bit ADCs As many as five dedicated 12 bit ADC channels As many as 29 dedicated 10 bit ADC channels Externally multiplexed channels Internal control to support generat...

Page 45: ...initiated by peripheral CPU periodic timer interrupt or eDMA channel request Peripheral DMA request sources possible from SPIs I2 C 10 bit ADC 12 bit ADC eMIOS and GPIOs Each eDMA channel able to opti...

Page 46: ...bytes Detection and flagging of LIN errors Sync field delimiter ID parity bit framing checksum and timeout errors Classic or extended checksum calculation Configurable break duration of up to 36 bit t...

Page 47: ...n count interface IEEE 1149 1 test access port TAP interface Backward compatible to standard JTAG IEEE 1149 1 2001 test access port TAP interface Supports boundary scan testing All JTAG pins reusable...

Page 48: ...Chapter 2 Introduction MPC5606BK Microcontroller Reference Manual Rev 2 48 Freescale Semiconductor This page is intentionally left blank...

Page 49: ...6_0000 0x0007_FFFF 128 Code flash memory array 0 0x0008_0000 0x0009_FFFF 128 Code flash memory array 0 0x000A_0000 0x000B_FFFF 128 Code flash memory array 0 0x000C_0000 0x000D_FFFF 128 Code flash memo...

Page 50: ...xC3FE_0000 0xC3FE_3FFF 16 MC_CGM 0xC3FE_4000 0xC3FE_7FFF 16 MC_RGM 0xC3FE_8000 0xC3FE_BFFF 16 MC_PCU 0xC3FE_C000 0xC3FE_FFFF 16 RTC API 0xC3FF_0000 0xC3FF_3FFF 16 PIT 0xC3FF_4000 0xFFDF_FFFF 981040 Re...

Page 51: ...0xFFF4_BFFF 16 INTC 0xFFF4_C000 0xFFF8_FFFF 272 Reserved 0xFFF9_0000 0xFFF9_3FFF 16 DSPI_0 0xFFF9_4000 0xFFF9_7FFF 16 DSPI_1 0xFFF9_8000 0xFFF9_BFFF 16 DSPI_2 0xFFF9_C000 0xFFF9_FFFF 16 DSPI_3 0xFFFA_...

Page 52: ...Chapter 3 Memory Map MPC5606BK Microcontroller Reference Manual Rev 2 52 Freescale Semiconductor This page is intentionally left blank...

Page 53: ...4 35 36 37 38 39 40 41 42 43 44 45 46 47 48 49 50 100 99 98 97 96 95 94 93 92 91 90 89 88 87 86 85 84 83 82 81 80 79 78 77 76 PB 3 PC 9 PC 14 PC 15 PA 2 PE 0 PA 1 PE 1 PE 8 PE 9 PE 10 PA 0 PE 11 VSS_H...

Page 54: ...15 PG 5 PG 4 PG 3 PG 2 PA 2 PE 0 PA 1 PE 1 PE 8 PE 9 PE 10 PA 0 PE 11 VSS_HV VDD_HV VSS_HV RESET VSS_LV VDD_LV VDD_BV PG 9 PG 8 PC 11 PC 10 PG 7 PG 6 PB 0 PB 1 PF 9 PF 8 PF 12 PC 6 PA 11 PA 10 PA 9 P...

Page 55: ...11 110 109 108 107 106 105 104 103 102 101 100 99 98 97 96 95 94 93 92 91 90 89 PA 11 PA 10 PA 9 PA 8 PA 7 PE 13 PF 14 PF 15 VDD_HV VSS_HV PG 0 PG 1 PH 3 PH 2 PH 1 PH 0 PG 12 PG 13 PA 3 PI 13 PI 12 PI...

Page 56: ...F1 AF2 AF3 GPIO 2 E0UC 2 MA 2 WKUP 3 4 SIUL eMIOS_0 ADC_0 WKUP I O I O O I S Tristate 5 9 17 PA 3 PCR 3 AF0 AF1 AF2 AF3 GPIO 3 E0UC 3 LIN5TX CS4_1 EIRQ 0 ADC1_S 0 SIUL eMIOS_0 LINFlex_5 DSPI_1 SIUL AD...

Page 57: ...2RX ADC1_S 3 SIUL eMIOS_0 I2 C_0 SIUL LINFlex_2 ADC_1 I O I O I O I I I J Tristate 75 108 132 PA 12 PCR 12 AF0 AF1 AF2 AF3 GPIO 12 E0UC 28 CS3_1 EIRQ 17 SIN_0 SIUL eMIOS_0 DSPI_1 SIUL DSPI_0 I O I O O...

Page 58: ...OS_0 I O O I O I O M Tristate 100 144 176 PB 3 PCR 19 AF0 AF1 AF2 AF3 GPIO 19 E0UC 31 SCL WKUP 11 4 LIN0RX SIUL eMIOS_0 I2 C_0 WKUP LINFlex_0 I O I O I O I I S Tristate 1 1 1 PB 4 PCR 20 AF0 AF1 AF2 A...

Page 59: ...0 PB 10 PCR 26 AF0 AF1 AF2 AF3 GPIO 26 WKUP 8 4 ADC0_S 2 ADC1_S 6 SIUL WKUP ADC_0 ADC_1 I O I I I J Tristate 40 54 62 PB 11 PCR 27 AF0 AF1 AF2 AF3 GPIO 27 E0UC 3 CS0_0 ADC0_S 3 SIUL eMIOS_0 DSPI_0 ADC...

Page 60: ...AF2 AF3 GPIO 34 SCK_1 CAN4TX DEBUG 0 EIRQ 5 SIUL DSPI_1 FlexCAN_4 SSCM SIUL I O I O O O I M Tristate 78 117 145 PC 3 PCR 35 AF0 AF1 AF2 AF3 GPIO 35 CS0_1 MA 0 DEBUG 1 EIRQ 6 CAN1RX CAN4RX SIUL DSPI_1...

Page 61: ...O I I S Tristate 2 2 2 PC 10 PCR 42 AF0 AF1 AF2 AF3 GPIO 42 CAN1TX CAN4TX MA 1 SIUL FlexCAN_1 FlexCAN_4 ADC_0 I O O O O M Tristate 22 28 36 PC 11 PCR 43 AF0 AF1 AF2 AF3 GPIO 43 MA 2 WKUP 5 4 CAN1RX CA...

Page 62: ...ADC_0 ADC_1 I I I I I Tristate 42 64 78 PD 2 PCR 50 AF0 AF1 AF2 AF3 GPIO 50 ADC0_P 6 ADC1_P 6 SIUL ADC_0 ADC_1 I I I I Tristate 43 65 79 PD 3 PCR 51 AF0 AF1 AF2 AF3 GPIO 51 ADC0_P 7 ADC1_P 7 SIUL ADC...

Page 63: ...SIUL ADC_0 ADC_1 I I I I Tristate 56 78 94 PD 10 PCR 58 AF0 AF1 AF2 AF3 GPIO 58 ADC0_P 14 ADC1_P 14 SIUL ADC_0 ADC_1 I I I I Tristate 57 79 95 PD 11 PCR 59 AF0 AF1 AF2 AF3 GPIO 59 ADC0_P 15 ADC1_P 15...

Page 64: ...20 PE 2 PCR 66 AF0 AF1 AF2 AF3 GPIO 66 E0UC 18 EIRQ 21 SIN_1 SIUL eMIOS_0 SIUL DSPI_1 I O I O I I M Tristate 89 128 156 PE 3 PCR 67 AF0 AF1 AF2 AF3 GPIO 67 E0UC 19 SOUT_1 SIUL eMIOS_0 DSPI_1 I O I O O...

Page 65: ...0 EIRQ 10 SIUL LINFlex_3 DSPI_1 eMIOS_1 SIUL I O O O I O I S Tristate 11 15 23 PE 11 PCR 75 AF0 AF1 AF2 AF3 GPIO 75 E0UC 24 CS4_1 LIN3RX WKUP 14 4 SIUL eMIOS_0 DSPI_1 LINFlex_3 WKUP I O I O O I I S Tr...

Page 66: ...tate 57 65 PF 3 PCR 83 AF0 AF1 AF2 AF3 GPIO 83 E0UC 13 CS1_2 ADC0_S 11 SIUL eMIOS_0 DSPI_2 ADC_0 I O I O O I J Tristate 58 66 PF 4 PCR 84 AF0 AF1 AF2 AF3 GPIO 84 E0UC 14 CS2_2 ADC0_S 12 SIUL eMIOS_0 D...

Page 67: ...4 LIN4RX SIUL DSPI_0 eMIOS_1 WKUP LINFlex_4 I O O I O I I S Tristate 39 47 PF 12 PCR 92 AF0 AF1 AF2 AF3 GPIO 92 E1UC 25 LIN5TX SIUL eMIOS_1 LINFlex_5 I O I O O M Tristate 35 43 PF 13 PCR 93 AF0 AF1 A...

Page 68: ...AF2 AF3 GPIO 100 E1UC 13 SCK_3 SIUL eMIOS_1 DSPI_3 I O I O I O M Tristate 6 14 PG 5 PCR 101 AF0 AF1 AF2 AF3 GPIO 101 E1UC 14 WKUP 18 4 SIN_3 SIUL eMIOS_1 WKUP DSPI_3 I O I O I I S Tristate 5 13 PG 6...

Page 69: ...UT_4 SIUL eMIOS_0 DSPI_4 I O I O O M Tristate 92 116 PG 13 PCR 109 AF0 AF1 AF2 AF3 GPIO 109 E0UC 27 SCK_4 SIUL eMIOS_0 DSPI_4 I O I O I O M Tristate 91 115 PG 14 PCR 110 AF0 AF1 AF2 AF3 GPIO 110 E1UC...

Page 70: ...AF3 GPIO 119 E1UC 9 CS3_2 MA 1 SIUL eMIOS_1 DSPI_2 ADC_0 I O I O O O M Tristate 137 165 PH 8 PCR 120 AF0 AF1 AF2 AF3 GPIO 120 E1UC 10 CS2_2 MA 0 SIUL eMIOS_1 DSPI_2 ADC_0 I O I O O O M Tristate 138 1...

Page 71: ...2 AF3 GPIO 129 E0UC 29 WKUP 24 4 SIUL eMIOS_0 WKUP I O I O I S Tristate 171 PI 2 PCR 130 AF0 AF1 AF2 AF3 GPIO 130 E0UC 30 SIUL eMIOS_0 I O I O S Tristate 170 PI 3 PCR 131 AF0 AF1 AF2 AF3 GPIO 131 E0UC...

Page 72: ...139 AF0 AF1 AF2 AF3 GPIO 139 ADC0_S 19 SIN_3 SIUL ADC_0 DSPI_3 I O I I J Tristate 111 PI 12 PCR 140 AF0 AF1 AF2 AF3 GPIO 140 CS0_3 ADC0_S 20 SIUL DSPI_3 ADC_0 I O I O I J Tristate 112 PI 13 PCR 141 AF...

Page 73: ...d in the PCR PA bitfields For this reason the value corresponding to an input only function is reported as 2 See Table 4 2 3 The RESET configuration applies during and after reset 4 All WKUP pins also...

Page 74: ...2 mode after reset which has TDO functionality The reset value of PCR OBE is 1 but this setting has no impact as long as this pad stays in AF2 mode After configuring this pad as GPIO PCR PA 0 output b...

Page 75: ...Force Alternate Boot mode on pin PA 9 ABS Alternate Boot Select on pin PA 8 Table 5 1 describes the configuration options The microcontroller has a weak pulldown on PA 9 and a weak pullup on PA 8 Thi...

Page 76: ...elow The entities to program are 16 bit Reset Configuration Half Word RCHW which contains A BOOT_ID field that must be correctly set to 0x5A in order to validate the boot sector 32 bit reset vector th...

Page 77: ...If no valid BOOT_ID within the RCHW was found the SSCM sets the CPU core instruction pointer to the BAM address and the core starts to execute the code to enter static mode as follows The core execut...

Page 78: ...nto the microcontroller SRAM Code may be downloaded using either FlexCAN or LINFlex RS232 After the SSCM has detected that serial boot mode has been requested execution is transferred to the BAM which...

Page 79: ...unity to get back into the microcontroller using the default private password of 0xFEED_FACE_CAFE_BEEF When configuring the private password each half word 16 bit must contain at least one 1 and one 0...

Page 80: ...p you require and configure the NVSCC0 1 values 3 Reprogram the shadow flash memory and NVPWD0 1 and NVSCC0 1 registers with your new values A POR is required before these will take effect CAUTION If...

Page 81: ...VSCC0 NVSCC1 0x55AA AND NVSCC0 NVSCC1 Enabled N A Private flash memory password and censored 0x55AA AND NVSCC0 NVSCC1 0x55AA AND NVSCC0 NVSCC1 Enabled NVPWD1 0 SSCM reads flash memory1 1 When the SSCM...

Page 82: ...ry boot mode FAB 0 Flash boot mode NVSCC0 NVSCC1 True Censored with no password access Locked out JTAG password details Enter password as NVPWD1 NVPWD0 False False False Both SC and CW 0x55AA CW 0x55A...

Page 83: ...mory boot mode is selected and a valid BOOT_ID is not located in one of the boot sectors by the SSCM 5 2 1 BAM software flow Figure 5 6 illustrates the BAM logic flow FAB 1 Serial boot mode NVSCC0 NVS...

Page 84: ...ed during reset There are two conditions where the boot mode is not considered valid and the BAM pushes the microcontroller into static mode after restoring the default configuration BMODE 011 flash m...

Page 85: ...sed for serial download see Table 5 6 5 2 1 2 Download and execute the new code From a high level perspective the download protocol follows these steps 1 Send the 64 bit password 2 Send the start addr...

Page 86: ...st determine which censorship mode the microcontroller is in and which password to use It does this by reading the PUB and SEC fields in the SSCM Status Register see Section 5 3 4 1 System Status Regi...

Page 87: ...is used the BAM code does a direct comparison between the serial password and 0xFEED_FACE_CAFE_BEEF 2 If the private password is used the BAM code does a direct comparison between the serial password...

Page 88: ...all the data has been copied to the SRAM 4 In the meantime the SSCM has compared the private password in flash with the serial download password the BAM code wrote into SSCM_PWCMPH and SSCM_PWCMPL 5...

Page 89: ...e password BAM running Yes BAM reads SSCM_STATUS SEC Serial password received Is SEC bit cleared BAM tasks SSCM tasks serial boot mode BAM writes received password to SSCM registers Upper 32 bits to S...

Page 90: ...ility The Start Address defines where the received data will be stored and where the MCU will branch after the download is finished The start address is 32 bit word aligned and the 2 least significant...

Page 91: ...sswords did not match the BAM code forces a static mode entry NOTE The watchdog is disabled at the start of BAM code execution In the case of an unexpected issue during BAM code execution the microcon...

Page 92: ...5 6 for examples of baud rate It uses the standard 11 bit identifier format detailed in FlexCAN 2 0A specification FlexCAN controller bit timing is programmed with 10 time quanta and the sample point...

Page 93: ...VLE bit 31 bit number of bytes CAN ID 0x002 32 bit store address VLE bit 31 bit number of bytes Load address is stored for future use Size of download are stored for future use Verify if VLE bit is s...

Page 94: ...BY power domain the System Status block is part of that domain Figure 5 12 SSCM block diagram 5 3 2 Features The SSCM includes these features System Configuration and Status Memory sizes status Microc...

Page 95: ...illegal 5 3 4 1 System Status Register SSCM_STATUS The System Status register is a read only register that reflects the current state of the system Table 5 10 SSCM memory map Address offset Register L...

Page 96: ...ith public password is allowed 1 Serial boot mode with public password is allowed 0 Serial boot mode with private flash memory password is allowed SEC Security Status This bit reflects the current sec...

Page 97: ...ions or because there is no Flash in the system 1 Code Flash is available 0 Code Flash is not available DTSZ Data Flash Size 0000 No Data Flash 0011 64 KB DVLD Data Flash Valid This bit identifies whe...

Page 98: ...gging when developing application code 1 Illegal accesses to peripherals produce a Prefetch or Data Abort exception 0 Illegal accesses to peripherals do not produce a Prefetch or Data Abort exception...

Page 99: ...ONFI G 9 Reserved Reserved Reserved 2 SSCM_STATUS 2 SSCM_STATUS 10 SSCM_MEMCONFI G 2 SSCM_MEMCONFI G 10 Reserved Reserved Reserved 3 SSCM_STATUS 3 SSCM_STATUS 11 SSCM_MEMCONFI G 3 SSCM_MEMCONFI G 11 R...

Page 100: ...4 5 6 7 8 9 10 11 12 13 14 15 R 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 W PWD_LO 31 16 Reset 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 16 17 18 19 20 21 22 23 24 25 26 27 28 29 30 31 R 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0...

Page 101: ...ds to be written as follows first the upper word to the SSCM_PWCMPH register then the lower word to the SSCM_PWCMPL register The SSCM compares the 64 bit password entered into the SSCM_PWCMPH SSCM_PWC...

Page 102: ...Chapter 5 Microcontroller Boot MPC5606BK Microcontroller Reference Manual Rev 2 102 Freescale Semiconductor This page is intentionally left blank...

Page 103: ...MPC5606BK Microcontroller Reference Manual Rev 2 Freescale Semiconductor 103 Clocks and power...

Page 104: ...MPC5606BK Microcontroller Reference Manual Rev 2 104 Freescale Semiconductor This page is intentionally left blank...

Page 105: ...or MPC5606BK 6 1 Clock architecture System clocks are generated from three sources Fast external crystal oscillator 4 16 MHz FXOSC Fast internal RC oscillator 16 MHz FIRC Frequency modulated phase loc...

Page 106: ...e 6 1 MPC5606BK Peripheral clock sources Peripheral Register gating address offset base 0xC3FD_C0C0 1 Peripheral set2 RPP_Z0H Platform none managed through ME mode DSPI_n 4 n n 0 5 2 FXOSC FIRC Clock...

Page 107: ...ernal oscillator driver and an external crystal circuitry It provides an output clock that can be provided to the FMPLL or used as a reference clock to specific modules depending on system needs The F...

Page 108: ...onfiguration is independent of the powerdown mode of the oscillator Table 6 2 shows the truth table of different oscillator configurations The FXOSC clock can be further divided by a configurable fact...

Page 109: ...escription OSCBYP Crystal Oscillator bypass This bit specifies whether the oscillator should be bypassed or not 0 Oscillator output is used as root clock 1 EXTAL is used as root clock EOCV End of Coun...

Page 110: ...pin and the oscillator status is forced to 1 The bypass configuration is independent of the powerdown mode of the oscillator Table 6 4 shows the truth table of different configurations of the oscilla...

Page 111: ...of count value to be used for comparison by the oscillator stabilization counter OSCCNT after reset or whenever it is switched on from the off state This counting period ensures that external oscilla...

Page 112: ...t SIRC_CTL SIRCTRIM and this field shows a value of zero Therefore be aware that the SIRC_CTL SIRCTRIM does not reflect the current trim value until you have written to this field Pay particular atten...

Page 113: ...FIRC_CTL FIRCTRIM field does not reflect the current trim value until you have written to it Pay particular attention to this feature when you initiate a read modify write operation on FIRC_CTL becau...

Page 114: ...0 0 0 0 0 16 17 18 19 20 21 22 23 24 25 26 27 28 29 30 31 R 0 0 0 FIRCDIV 0 0 FIRCON_STDBY 0 0 0 0 0 W RESET 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 Figure 6 5 FIRC Oscillator Control Register FIRC_CTL Table...

Page 115: ...device with a frequency higher than allowed no hardware check The FMPLL block diagram is shown in Figure 6 6 Figure 6 6 FMPLL block diagram 6 7 3 Features The FMPLL has the following major features In...

Page 116: ...isor mode only 6 7 5 1 Control Register CR 1 FMPLL_x are mapped through the ME_CGM register slot Table 6 8 FMPLL memory map Base address 0xC3FE_00A0 Address offset Register Location 0x0 Control Regist...

Page 117: ...serial communications until the division has finished UNLOCK_ONCE This bit is a sticking indication of FMPLL loss of lock condition UNLOCK_ONCE is set when the FMPLL loses lock Whenever the FMPLL reac...

Page 118: ...tput divide ratios ODF 1 0 Output divide ratios 00 Divide by 2 01 Divide by 4 10 Divide by 8 11 Divide by 16 Table 6 12 Loop divide ratios NDIV 6 0 Loop divide ratios 0000000 0011111 0100000 Divide by...

Page 119: ...YPASS signal is used to bypass the strobe signal used inside FMPLL to latch the correct values for control bits INC_STEP MOD_PERIOD and SPRD_SEL 0 Strobe is used to latch FMPLL modulation control bits...

Page 120: ...n 0 Frequency modulation disabled 1 Frequency modulation enabled INC_STEP Increment step The INC_STEP field is the binary equivalent of the value incstep derived from following formula where md repres...

Page 121: ...aveform is always a triangle wave and its shape is not programmable FM mode is activated in two steps 1 Configure the FM mode characteristics MOD_PERIOD INC_STEP 2 Enable the FM mode by programming bi...

Page 122: ...7 6 4 Powerdown mode To reduce consumption the FMPLL can be switched off when not required by programming the registers ME_x_MC on the MC_ME module 6 7 7 Recommendations To avoid any unpredictable beh...

Page 123: ...rn can then switch to a SAFE mode where it uses the default safe clock source FIRC resets the device or generates the interrupt according to the system needs It can also monitor the external crystal o...

Page 124: ...Meter CMU_FDR FMPLL Supervisor OLR_evt FHH_FLL_OR_evt_a XXOSC ON OFF From MC_ME FMPLL ON OFF From MC_ME MUX1 CKSEL1 1 0 00 01 10 11 FIRC_clk FIRC_clk SIRC_clk SXOSC_clk FXOSC_clk FMPLL FMPLL hfref OR...

Page 125: ...d when the FXOSC frequency is greater than FIRC 2RCDIV 0 5 MHz 6 8 4 2 FMPLL clock monitor The fFMPLL_clk can be monitored by programming bit CME of the CMU_CSR register to 1 The FMPLL_clk monitor sta...

Page 126: ...ure starts when bit SFM Start Frequency Measure in the CMU_CSR is set to 1 The measurement duration is given by the CMU_MDR in numbers of clock cycles of the selected clock source with a width of 20 b...

Page 127: ...re can only set this bit to start a clock frequency measure It is reset by hardware when the measure is ready in the CMU_FDR register 0 Frequency measurement completed or not yet started 1 Frequency m...

Page 128: ...D Measured frequency bits This register shows the measured frequency fx with respect to fFXOSC The measured value is given by the following formula fx fFXOSC MD n where n is the value in CMU_FDR regis...

Page 129: ...0 0 0 0 0 0 0 0 0 0 0 0 0 Figure 6 15 Low Frequency Reference Register FMPLL CMU_LFREFR Table 6 20 CMU_LFREFR field descriptions Field Description LFREF Low Frequency reference value This field deter...

Page 130: ...ng 1 0 No FLL event 1 FLL event is pending OLRI Oscillator frequency lower than RC frequency event This bit is set by hardware when fFXOSC_clk is lower than FIRC_clk 2RCDIV frequency and FXOSC_clk is...

Page 131: ...sources to supply the system clock The MC_ME controls the system clock selection see Chapter 8 Mode Entry Module MC_ME for more details A set of MC_CGM registers controls the clock dividers which are...

Page 132: ...includes the following features Generates system and peripheral clocks Selects and enables disables the system clock supply from system clock sources according to MC_ME control Output Clock Selector...

Page 133: ...off chip use and or observation 7 5 Memory map and register definition NOTE Any access to unused registers as well as write accesses to read only registers will Not change register content Table 7 1 M...

Page 134: ...13 14 15 16 17 18 19 20 21 22 23 24 25 26 27 28 29 30 31 0xC3FE _0000 0xC3FE _001C FXOSC registers 0xC3FE _0020 0xC3FE _003C reserved 0xC3FE _0040 0xC3FE _005C SXOSC registers 0xC3FE _0060 0xC3FE _00...

Page 135: ...ed 0xC3FE _0160 0xC3FE _017C reserved 0xC3FE _0180 0xC3FE _019C reserved 0xC3FE _01A0 0xC3FE _01BC reserved 0xC3FE _01C0 0xC3FE _01DC reserved 0xC3FE _01E0 0xC3FE _01FC reserved 0xC3FE _0200 0xC3FE _0...

Page 136: ...ed 0xC3FE _0280 0xC3FE _029C reserved 0xC3FE _02A0 0xC3FE _02BC reserved 0xC3FE _02C0 0xC3FE _02DC reserved 0xC3FE _02E0 0xC3FE _02FC reserved 0xC3FE _0300 0xC3FE _031C reserved 0xC3FE _0320 0xC3FE _0...

Page 137: ...ved 0xC3FE _0370 CGM_OC_EN R 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 W R 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 EN W 0xC3FE _0374 CGM_OCDS_ SC R 0 0 SELDIV SELCTL 0 0 0 0 0 0 0 0 W R 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 W...

Page 138: ...0 W Reset 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 16 17 18 19 20 21 22 23 24 25 26 27 28 29 30 31 R 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 EN W Reset 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 Figure 7 2 Output Clock Enable Reg...

Page 139: ...ion 01 output selected Output Clock divided by 2 10 output selected Output Clock divided by 4 11 output selected Output Clock divided by 8 SELCTL Output Clock Source Selection Control This value selec...

Page 140: ...ed Address 0xC3FE_037C Access User read Supervisor read write Test read write 0 1 2 3 4 5 6 7 8 9 10 11 12 13 14 15 R DE0 0 0 0 DIV0 DE1 0 0 0 DIV1 W Reset 1 0 0 0 0 0 0 0 1 0 0 0 0 0 0 0 16 17 18 19...

Page 141: ...cess to the DIV2 field is ignored and the peripheral set 3 clock remains disabled Address 0xC3FE_0380 Access User read Supervisor read write Test read write 0 1 2 3 4 5 6 7 8 9 10 11 12 13 14 15 R 0 0...

Page 142: ...ion Module MC_RGM for more details The safe clock request forces the selector to select the 16 MHz int RC osc as the system clock and to ignore the system clock select Figure 7 7 MC_CGM System Clock G...

Page 143: ...peripheral clocks The MC_CGM has the following control registers for built in dividers Section 7 5 3 1 System Clock Divider Configuration Registers CGM_SC_DC0 2 The reset value of all counters is 1 If...

Page 144: ...e output clock generation PA 0 see Figure 7 8 This signal is generated by utilizing one of the 3 stage ripple counter outputs or the selected signal without division The non divided signal is not guar...

Page 145: ...registers accessible for the application Figure 8 1 shows the MC_ME block diagram Figure 8 1 MC_ME block diagram 8 1 1 Features The MC_ME includes the following features Control of the available mode...

Page 146: ...ilable for the embedded software to take control of the device It manages hardware initialization of chip configuration voltage regulators oscillators PLLs and flash modules System reset assertion fro...

Page 147: ...abled It may be configured to switch off most of the peripherals including oscillator for efficient power management at the cost of higher wakeup latency Software request from RUN0 3 System reset asse...

Page 148: ...ME_RUN0_MC RUN0 Mode Configuration word read read write read write on page 161 0xC3FD _C034 ME_RUN1_MC RUN1 Mode Configuration word read read write read write on page 161 0xC3FD _C038 ME_RUN2_MC RUN2...

Page 149: ...0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 W R 0 0 0 0 0 0 0 0 0 0 0 0 M_ICONF M_IMODE M_SAFE M_MTC W 0xC3FD _C014 ME_IMTS R 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 W R 0 0 0 0 0 0 0 0 0 0 0 S_MTI S_MRI S_DMA S_NMA S_SEA...

Page 150: ...0 0 0 0 0 PDO 0 0 MVRON DFLAON CFLAON W 0xC3FD _C028 ME_SAFE_M C R 0 0 0 0 0 0 0 0 PDO 0 0 MVRON DFLAON CFLAON W R 0 0 0 0 0 0 0 0 0 FIRCON SYSCLK W 0xC3FD _C02C ME_DRUN_M C R 0 0 0 0 0 0 0 0 PDO 0 0...

Page 151: ...UN0 0101 RUN1 0110 RUN2 0111 RUN3 1000 HALT 1001 reserved 1010 STOP 1011 reserved 1100 reserved 1101 1110 reserved 1111 reserved S_MTRANS Mode transition status 0 Mode transition process is not active...

Page 152: ...e flash is in normal mode and available for use S_FIRC fast internal RC oscillator 16 MHz status 0 fast internal RC oscillator 16 MHz is not stable 1 fast internal RC oscillator 16 MHz is providing a...

Page 153: ...with key and second time with inverted key These bits are automatically updated by hardware while entering SAFE on hardware request Also while exiting from the HALT and STOP modes on hardware exit eve...

Page 154: ...mode enable 0 RUN1 mode is disabled 1 RUN1 mode is enabled RUN0 RUN0 mode enable 0 RUN0 mode is disabled 1 RUN0 mode is enabled DRUN DRUN mode enable 0 DRUN mode is disabled 1 DRUN mode is enabled SAF...

Page 155: ...enters SAFE mode on hardware requests generated in the system It is cleared by writing a 1 to this bit 0 No SAFE mode interrupt occurred 1 SAFE mode interrupt is pending I_MTC Mode transition complete...

Page 156: ...eld Descriptions Field Description S_MTI Mode Transition Illegal status This bit is set whenever a new mode is requested while some other mode transition process is active S_MTRANS is 1 Please see Sec...

Page 157: ...It is cleared by writing a 1 to this bit 0 Target mode requested is an existing mode 1 Target mode requested is a non existing mode S_SEA SAFE Event Active status This bit is set whenever the device...

Page 158: ...rdware SAFE mode request has been triggered It is cleared when the hardware SAFE mode request has been cleared 0 A SAFE mode request is not active 1 A SAFE mode request is active FIRC_SC FIRC State Ch...

Page 159: ...and half word write accesses are not allowed to this register Address 0xC3FD_C020 Access User read Supervisor read write Test read write R 0 0 0 0 0 0 0 0 PDO 0 0 MVRON DFLAON CFLAON W Reset 0 0 0 0...

Page 160: ...e and half word write accesses are not allowed to this register NOTE The values of CFLAON and DFLAON are retained through STANDBY mode Address 0xC3FD_C028 Access User read Supervisor read write Test r...

Page 161: ...not allowed to this register 8 3 1 14 STOP Mode Configuration Register ME_STOP_MC This register configures system behavior during STOP mode Please see Table 8 11 for details NOTE Byte and half word wr...

Page 162: ...mode 00 Reserved 01 Data flash is in power down mode 10 Data flash is in low power mode 11 Data flash is in normal mode Note If the flash memory is to be powered down in any mode then your software m...

Page 163: ...e corresponding ME_ mode _MC register The mode transition request may require a number of cycles depending on the programmed configuration and software should check the S_CURRENT_MODE bit field and th...

Page 164: ...system see Chapter 9 Reset Generation Module MC_RGM for details Transition to this mode is instantaneous and the system remains in this mode until the reset sequence is finished The mode configuration...

Page 165: ...MC_RGM because of some potentially recoverable hardware failure in the system see Chapter 9 Reset Generation Module MC_RGM for details As soon as any of the above events has occurred a SAFE mode tran...

Page 166: ...ip test routines NOTE As flash modules can be configured to a low power or power down state in these modes software must ensure that the code will execute from RAM before it changes to this mode 8 4 2...

Page 167: ...ration information for this mode is provided by the ME_STOP_MC register This mode is fully configurable and the ME_STOP_MC register should be programmed according to the system needs The flashes can b...

Page 168: ...MCTL register is passed to the MC_RGM which generates a global system reset and initiates the reset sequence The RESET mode request has the highest priority and the MC_ME is kept in the RESET mode dur...

Page 169: ...ests the processor to enter its halted state The processor acknowledges its halt state request after completing all outstanding bus transactions If on completion of the Peripheral Clocks Disable the m...

Page 170: ...n voltage regulator switch on On completion of the Target mode request if the main voltage regulator needs to be switched on from its off state based on the MVRON bit of the ME_ current mode _MC and M...

Page 171: ...s completed 8 4 3 12 System clock switching Based on the SYSCLK bit field of the ME_ current mode _MC and ME_ target mode _MC registers if the target and current system clock configurations differ the...

Page 172: ...low power state and waits for the deassertion of flash ready status signal The exact low power mode status of the flash modules is updated in the S_CFLA and S_DFLA bit fields of the ME_GS register Thi...

Page 173: ...TARGET_MODE of the ME_MCTL register when All the updated status bits in the ME_GS register match the configuration specified in the ME_ target mode _MC register Power sequences are done Clock disable...

Page 174: ...rget Mode Request Write ME_MCTL register SAFE mode request interrupt wakeup event Peripheral Clocks Disable Clock sources Switch On System Clock Switching Main VREG Switch On FLASH Switch On Pad Proce...

Page 175: ...e _MC registers violating the protection rules mentioned in the Section 8 4 4 Protection of mode configuration registers the interrupt pending bit I_ICONF of the ME_IS register is set and an interrupt...

Page 176: ...instant these requests to return to RUN0 3 modes are always valid In order to avoid any unwanted lockup of the device modes software can abort a mode transition by requesting the parent mode if for e...

Page 177: ...em completes a mode transition fully i e the S_MTRANS bit of ME_GS register transits from 1 to 0 the interrupt pending bit I_MTC of the ME_IS register is set and interrupt request is generated if the...

Page 178: ...m START of mode change Config for target mode okay Write ME_ target mode _MC register N Y Write ME_MCTL with target mode and key Write ME_MCTL with target mode and inverted key Start timer S_MTRANS cl...

Page 179: ...different reset sources and manages the reset sequence of the device It provides a register interface and the reset sequencer The different registers are available to monitor and control the device re...

Page 180: ...resets management Functional resets management Signalling of reset events after each reset sequence reset status flags Conversion of reset events to SAFE mode or interrupt request eventsChapter 8 Mode...

Page 181: ...ernal reset When a reset is triggered the MC_RGM state machine is activated and proceeds through the different phases i e PHASEn states Each phase is associated with a particular device reset being pr...

Page 182: ...write1 1 individual bits cleared on writing 1 read write1 on page 208 0xC3FE _4004 RGM_FERD Functional Event Reset Disable half word read read read on page 209 0xC3FE _4006 RGM_DERD Destructive Event...

Page 183: ...e accessed as a word at address 0xC3FE_4018 as a half word at address 0xC3FE_401A or as a byte at address 0xC3FE_401B 0xC3FE _4004 RGM_ FERD RGM_ DERD R D_EXR 0 0 0 0 0 0 CHKSTOP W R 0 0 0 0 0 0 0 0 0...

Page 184: ...completed Address 0xC3FE_4000 Access User read Supervisor read write Test read write R F_EXR 0 0 0 0 0 0 CHKSTOP W w1c POR 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 Figure 9 2 Functional Event Status Register...

Page 185: ...nctional reset source is disabled the associated functional event will trigger either a SAFE mode request or an interrupt request see Section 9 3 1 5 Functional Event Alternate Request Register RGM_FE...

Page 186: ...accessed in read only in user mode 9 3 1 6 Destructive Event Alternate Request Register RGM_DEAR This register defines an alternate request to be generated when a reset on a destructive event has been...

Page 187: ...This register enables the generation of an external reset on functional reset It can be accessed in read write in either supervisor mode or test mode It can be accessed in read in user mode Address 0...

Page 188: ...e reset sequence is shown in Figure 9 10 Table 9 10 Functional Bidirectional Reset Enable Register RGM_FBRE field descriptions Field Description BE_EXR Bidirectional Reset Enable for External Reset 0...

Page 189: ...stable VREG voltage okay done duration 10 fast internal RC oscillator 16 MHz clock cycles duration fast internal RC oscillator 16 MHz clock cycles code and data flash initialization done duration 40...

Page 190: ...need to be done in PHASE0 are completed A minimum of 3 fast internal RC oscillator 16 MHz clock cycles have elapsed since power up completion and the last enabled destructive reset event 9 4 1 2 PHASE...

Page 191: ...ive reset indicates that an event has occurred after which critical register or memory content can no longer be guaranteed The status flag associated with a given destructive reset event RGM_DES F_ de...

Page 192: ...itical register and memory content is still intact The status flag associated with a given functional reset event RGM_FES F_ functional reset bit is set when the functional reset is asserted and the p...

Page 193: ...PHASE0 it is ignored and the MC_RGM will not send any safe mode interrupt request to the MC_ME The same is true for masked functional reset events during PHASE1 9 4 6 Boot mode capturing The MC_RGM s...

Page 194: ...Chapter 9 Reset Generation Module MC_RGM MPC5606BK Microcontroller Reference Manual Rev 2 194 Freescale Semiconductor This page is intentionally left blank...

Page 195: ...power domain reaches its operational voltage Power domains are controlled on a device mode basis For each mode software can configure whether a power domain is connected to the supply voltage power u...

Page 196: ...omains Support for device modes RESET DRUN SAFE TEST RUN0 3 HALT STOP and STANDBY for further mode details please see Power states updating on each mode change and on system wakeup A handshake mechani...

Page 197: ...ead read write read write on page 201 0xC3FE _8010 PCU_PCONF4 Power Domain 4 Configuration word read read write read write on page 201 0xC3FE _8014 PCU_PCONF5 Power Domain 5 Configuration word read re...

Page 198: ...0 0 0 0 0 0 0 0 0 W R 0 0 STBY0 0 0 STOP 0 HALT RUN3 RUN2 RUN1 RUN0 DRUN SAFE TEST RST W 0xC3FE _8008 PCU_PCONF2101 2456789 R 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 W R 0 0 STBY0 0 0 STOP 0 HALT RUN3 RUN2 RU...

Page 199: ...omain 0 is the always on power domain and includes the MC_PCU none of its bits are programmable This register is available for completeness reasons 0xC3FE _8080 0xC3FE _80FC 0xC3FE _8100 0xC3FE _BFFC...

Page 200: ...N1 mode 0 Power domain off 1 Power domain on RUN2 Power domain control during RUN2 mode 0 Power domain off 1 Power domain on RUN3 Power domain control during RUN3 mode 0 Power domain off 1 Power domai...

Page 201: ...ister PCU_PCONF2 This register defines for power domain 2 whether it is on or off in each device mode The bit field description is the same as in Table 10 3 10 3 1 4 Power Domain 2 10123456789 Configu...

Page 202: ...wer domain is reflected by the bits in the PCU_PSTAT register Address 0xC3FE_800C Access User read write Supervisor read write Test read write R 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 W Reset 0 0 0 0 0 0 0 0...

Page 203: ...nfigurations for all power domains It compares the settings in the PCU_PCONFn registers for the new mode with the settings for the current mode If the configuration for a power domain differs between...

Page 204: ...he power supply Among others power domain 1 contains the platform and the MC_ME Therefore this mode differs from all other user system modes Once STANDBY is entered it can only be left via a system wa...

Page 205: ...omain is lost 10 4 4 3 Power saving for memories during STANDBY mode All memories that are not powered down during STANDBY mode automatically enter a power saving state No software configuration is re...

Page 206: ...y But power is only saved during the time a power domain is disconnected from the supply Increased power is required when a power domain is reconnected to the power supply Additional power is required...

Page 207: ...der to provide a stable low voltage digital supply to the device Capacitances should be placed on the board as near as possible to the associated pins The regulator has two digital domains one for the...

Page 208: ...s required to initialize the device during supply rise POR works only on the rising edge of the main supply To ensure its functioning during the following rising edge of the supply it is reset by the...

Page 209: ...S_HV_ADC power pins Voltage values should be aligned with VDD_HV_ADC VSS_HV_ADC Refer to data sheet for details 3 BV high voltage external power supply for voltage regulator module This must be provid...

Page 210: ...ballasts The HV supply for both ballasts is shorted through double bonding LV_COR Low voltage supply for the core It is also used to provide supply for FMPLL through double bonding LV_FLAn Low voltage...

Page 211: ...OR1HV POR2HV nbypass HPPD LPPD Vss VREG RTC CAN sampler WKPU CFLASH DFLASH PE0 PE9 PE11 RC Dig Wakeup Pads SIUL SSCM Reset e200z0h platform PA0 PA1 PA2 PJ4 VDD12 330nF CGM CGL ME Peripheral Set PLL Pe...

Page 212: ...Chapter 11 Voltage Regulators and Power Supplies MPC5606BK Microcontroller Reference Manual Rev 2 212 Freescale Semiconductor This page is intentionally left blank...

Page 213: ...to ensure no leakage from floating inputs Table 12 1 Wakeup vector mapping Wakeup number Port SIU PCR Port input function1 can be used in conjunction with WKPU function WKPU IRQ to INTC IRQ WISR Regis...

Page 214: ...WKPU28 PD1 PCR49 EIF28 3 1 This column does not contain an exhaustive list of functions on that pin Rather it includes peripheral communication functions such as CAN and LINFlex Rx that could be used...

Page 215: ...machine check request Edge detection External wakeup interrupt support with Four system interrupt vectors for as many as 29 interrupt sources Analog glitch filter per each wakeup line Independent inte...

Page 216: ...Wake up signal input should be terminated by using an external pullup or pulldown or by internal pullup enabled at WKPU_WIPUER Also care has to be taken on packages where the Wake up signal inputs ar...

Page 217: ...0 0 0 0 0 0 0 0 0 0 0 16 17 18 19 20 21 22 23 24 25 26 27 28 29 30 31 R 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 W Reset 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 Figure 12 2 NMI Status Flag Register NSR Table 12 3 NSR...

Page 218: ...ocked by a system reset Writing a 0 has no effect NDSS0 NMI Destination Source Select 00 Non maskable interrupt 01 Critical interrupt 10 Machine check request 11 Reserved no NMI critical interrupt or...

Page 219: ...have corresponding bits 12 4 5 Interrupt Request Enable Register IRER This register is used to enable the interrupt messaging from the wakeup interrupt pads to the interrupt controller Offset 0x14 Acc...

Page 220: ...ailable in 144 pin LQFP W w1c Reset 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 Figure 12 5 Interrupt Request Enable Register IRER Table 12 6 IRER field descriptions Field Descript...

Page 221: ...23 not available in 144 pin LQFP W Reset 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 Figure 12 7 Wakeup Interrupt Rising Edge Event Enable Register WIREER Table 12 8 WIREER field...

Page 222: ...LQFP W Reset 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 Figure 12 9 Wakeup Interrupt Filter Enable Register WIFER Table 12 10 WIFER field descriptions Field Description IFE x Ext...

Page 223: ...the capturing of a second event per NMI input before the interrupt is cleared thus reducing the chance of losing an NMI event Each NMI passes through a bypassable analog glitch filter NOTE Glitch filt...

Page 224: ...cleared by writing a 1 to them this prevents inadvertent overwriting of other flags in the register The status flag is set whenever an NMI event is detected The overrun flag is set whenever an NMI ev...

Page 225: ...the user to recognize external interrupts with an active rising edge an active falling edge or both edges being active NOTE Writing a 0 to both IREE x and IFEE x disables the external interrupt functi...

Page 226: ...he on chip wakeups with the external ones to generate a single wakeup to the system 12 5 4 1 On chip wakeup management In order to allow software to determine the wakeup source at one location on chip...

Page 227: ...o exit a low power mode or an interrupt request 13 2 Features Features of the RTC API include Three selectable counter clock sources SIRC 128 kHz SXOSC 32 KHz FIRC 16 MHz Optional 512 prescaler and op...

Page 228: ...Semiconductor Figure 13 1 RTC API block diagram 0 1 2 CLKSEL 0 1 3 SIRC FIRC SXOSC CNTEN RTCCNT RTCVAL 10 21 RTCF RTCIE RTC interrupt offset reg 22 31 API wakeup load 22 31 APIVAL APIEN reset reset 3...

Page 229: ...et with the exception of software watchdog reset The RTC provides a configurable divider by 512 to be optionally used when FIRC source is selected 13 4 Modes of operation 13 4 1 Functional mode There...

Page 230: ...bit which determines whether other registers are accessible in supervisor mode or user mode NOTE RTCSUPV register is accessible only in supervisor mode Table 13 1 RTC API register map Base address 0xC...

Page 231: ...ontrol Register RTCC Table 13 3 RTCC field descriptions Field Description CNTEN Counter Enable The CNTEN field enables the RTC counter Making CNTEN bit 0 has the effect of asynchronously resetting syn...

Page 232: ...Select This field selects the clock source for the RTC CLKSEL may only be updated when CNTEN is 0 The user should ensure that oscillator is enabled before selecting it as a clock source for RTC 00 SXO...

Page 233: ...scriptions Field Description RTCF RTC Interrupt Flag The RTCF bit indicates that the RTC counter has reached the counter value matching RTCVAL RTCF is cleared by writing a 1 to RTCF Writing a 0 to RTC...

Page 234: ...alue in the RTCC RTCVAL field then the RTCS RTCF interrupt flag bit is set after proper clock synchronization If the RTCC RTCIE interrupt enable bit is set then the RTC interrupt request is generated...

Page 235: ...nt to calculate an offset When the counter reaches the offset count a interrupt and or wakeup request is generated Then the offset value is recalculated and again re triggers a new request when the ne...

Page 236: ...Chapter 13 Real Time Clock Autonomous Periodic Interrupt RTC API MPC5606BK Microcontroller Reference Manual Rev 2 236 Freescale Semiconductor This page is intentionally left blank...

Page 237: ...econd frame the CAN Sampler stores samples of the 48 bits or skips the first frame and stores samples of the 48 bits of second frame using the 16 MHz fast internal RC oscillator and the 5 bit clock pr...

Page 238: ...0 0 0 16 17 18 19 20 21 22 23 24 25 26 27 28 29 30 31 R RX_COMPLETE BUSY ACTIVE_CK 0 0 0 MODE CAN_RX_SEL BRP CAN_SMPLR_EN W Reset 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 Figure 14 2 Control Register CR Table...

Page 239: ...re the first identifier is ignored and the sampling is performed on the first falling edge of after interframe space CAN_RX_SEL These bits determine which RX bit is sampled 000 Rx0 is selected 001 Rx1...

Page 240: ...l bit of the second frame including the SOF bit These samples are stored in consecutive addresses of the 12 32 internal registers RX_COMPLETE bit is set to 1 indicating that sampling is complete Softw...

Page 241: ...bits 5 1 in Control register The reset value of BRP is 00000 and can be set to maximum value of 11111 which gives a prescale value of BRP 1 thus providing a BRP range of 1 to 32 Maximum bit rate suppo...

Page 242: ...Chapter 14 CAN Sampler MPC5606BK Microcontroller Reference Manual Rev 2 242 Freescale Semiconductor This page is intentionally left blank...

Page 243: ...MPC5606BK Microcontroller Reference Manual Rev 2 Freescale Semiconductor 243 Core platform modules...

Page 244: ...MPC5606BK Microcontroller Reference Manual Rev 2 244 Freescale Semiconductor This page is intentionally left blank...

Page 245: ...Memory Access stage 3 and Register Writeback stage 4 stages operate in an overlapped fashion allowing single clock instruction execution for most instructions The integer execution unit consists of a...

Page 246: ...not incur any pipeline bubbles for most cases The Condition Register unit supports the condition register CR and condition register operations defined by the Power Architecture platform The condition...

Page 247: ...VLE only programmer s model Single issue 32 bit CPU Implements the VLE APU for reduced code footprint In order execution and retirement CPU CONTROL LOGIC LOAD DATA ADDRESS STORE UNIT INSTRUCTION UNIT...

Page 248: ...y Synthesizeable full MuxD scan design ABIST MBIST for optional memory arrays 15 4 1 Instruction unit features The features of the e200 Instruction unit are 32 bit instruction fetch path supports fetc...

Page 249: ...ters and programmer s model This section describes the registers implemented in the e200z0h cores It includes an overview of registers defined by the Power Architecture platform highlighting differenc...

Page 250: ...the Power Architecture specification In this document register bits are sometimes numbered from bit 0 Most Significant Bit to 31 Least Significant Bit rather than the Book E numbering scheme of 32 63...

Page 251: ...Data Address Compare DAC1 DAC2 SPR 316 SPR 317 1 These e200 specific registers may not be supported by other Power Architecture processors 2 Optional registers defined by the Power Architecture techno...

Page 252: ...Chapter 15 e200z0h Core MPC5606BK Microcontroller Reference Manual Rev 2 252 Freescale Semiconductor This page is intentionally left blank...

Page 253: ...MA source to any available eDMA channel with total of as many as 32 request sources DMA supports the following functionality Scatter Gather Channel Linking Inner Loop Offset Arbitration Fixed Group fi...

Page 254: ...ion Programmable source destination addresses transfer size plus support for enhanced addressing modes Transfer control descriptor organized to support two deep nested transfer operations An inner dat...

Page 255: ...Memory map The eDMA memory map is shown in Table 16 1 The eDMA base address is 0xFFF4_4000 The address of each register is given as an offset to the eDMA base address Registers are listed in address...

Page 256: ...n page 269 0x0104 EDMA_CPR4 eDMA channel 4 priority register on page 269 0x0105 EDMA_CPR5 eDMA channel 5 priority register on page 269 0x0106 EDMA_CPR6 eDMA channel 6 priority register on page 269 0x0...

Page 257: ...2 and Table 16 2 for the EDMA_CR definition 0x1060 TCD03 eDMA transfer control descriptor 03 on page 271 0x1080 TCD04 eDMA transfer control descriptor 04 on page 271 0x10A0 TCD05 eDMA transfer contro...

Page 258: ...nored In addition to cancelling the transfer the ECX treats the cancel as an error condition thus updating the EDMA_ESR register and generating an optional error interrupt see Section 16 3 2 2 DMA Err...

Page 259: ...reported as the channel is activated and assert an error interrupt request if enabled When properly enabled a scatter gather configuration error is reported when the scatter gather operation begins a...

Page 260: ...me error condition Offset 0x0004 Access Read 0 1 2 3 4 5 6 7 8 9 10 11 12 13 14 15 R VLD 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 W RESET 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 16 17 18 19 20 21 22 23 24 25 26 27 28 29...

Page 261: ...s a configuration error detected in the TCD daddr field TCD daddr is inconsistent with TCD dsize DOE Destination Offset Error 0 No destination offset configuration error 1 The last recorded error was...

Page 262: ...o the EDMA_SEEIR and EDMA_CEEIR registers The EDMA_SEEIR and EDMA_CEEIR registers are provided so that the error interrupt enable for a single channel can be modified without the performing a read mod...

Page 263: ...0 0 0 0 W RESET 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 16 17 18 19 20 21 22 23 24 25 26 27 28 29 30 31 R EEI15 EEI14 EEI13 EEI12 EEI11 EEI10 EEI09 EEI08 EEI07 EEI06 EEI05 EEI04 EEI03 EEI02 EEI01 EEI00 W RESE...

Page 264: ...EIRL to enable the error interrupt for a given channel The data value on a register write causes the corresponding bit in the EDMA_EEIRL to be set Setting bit 1 SEEI 0 provides a global set function f...

Page 265: ...equest for a given channel The given value on a register write causes the corresponding bit in the EDMA_IRQRL to be cleared Setting bit 1 CINT 0 provides a global clear function forcing the entire con...

Page 266: ...ART bit in the TCD of the given channel The data value on a register write causes the START bit in the corresponding transfer control descriptor to be set Setting bit 1 SSB 0 provides a global set fun...

Page 267: ...o the interrupt controller INTC During the execution of the interrupt service routine associated with any given channel software must clear the appropriate bit negating the interrupt request Typically...

Page 268: ...gister can also be polled A non zero value indicates the presence of a channel error regardless of the state of the EDMA_EEIR The EDMA_ESR VLD bit is a logical OR of all bits in this register and it p...

Page 269: ...0 0 0 16 17 18 19 20 21 22 23 24 25 26 27 28 29 30 31 R ERR15 ERR14 ERR13 ERR12 ERR11 ERR10 ERR09 ERR08 ERR07 ERR06 ERR05 ERR04 ERR03 ERR02 ERR01 ERR00 W RESET 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 Figure...

Page 270: ...suspended and the higher priority channel will be serviced Nested preemption attempting to preempt a preempting channel is not supported After a preempting channel begins execution it cannot be preem...

Page 271: ...st 1 Channel n can be temporarily suspended by the service request of a higher priority channel DPA Disable Preempt Ability 0 Channel n can suspend a lower priority channel 1 Channel n cannot suspend...

Page 272: ...8 9 10 11 12 13 14 15 16 17 18 19 20 21 22 23 24 25 26 27 28 29 30 31 0x0000 SADDR 0x0004 SMOD SSIZE DMOD DSIZE SOFF 0x0008 NBYTES1 1 The fields implemented in Word 2 depend on whether EDMA_CR EMLM is...

Page 273: ...7 SSIZE 0 2 Source data transfer size 000 8 bit 001 16 bit 010 32 bit 011 Reserved 100 16 byte 32 bit 4 beat WRAP4 burst 101 32 byte 32 bit 8 beat WRAP8 burst 110 Reserved 111 Reserved The attempted s...

Page 274: ...the daddr 66 85 0x8 2 21 MLOFF or NBYTES 1 0 19 Inner minor byte transfer count or Minor loop offset If both SMLOE and DMLOE are cleared this field is part of the byte transfer count If either SMLOE...

Page 275: ...is exhausted TCD bits 161 175 are used to form a 15 bit CITER field Otherwise After the minor loop is exhausted the DMA engine initiates a channel service request at the channel defined by CITER LINKC...

Page 276: ...pressed in favor of the MAJOR E_LINK channel linking 0 The channel to channel linking is disabled 1 The channel to channel linking is enabled Note When the TCD is first loaded by software this field m...

Page 277: ...5 by setting that channel s TCD START bit 248 0x1C 24 DONE Channel done This flag indicates the eDMA has completed the outer major loop It is set by the DMA engine as the CITER count reaches zero it i...

Page 278: ...nable an interrupt when major counter is half complete If this flag is set the channel generates an interrupt request by setting the appropriate bit in the EDMA_ERQRL when the current major iteration...

Page 279: ...is exhausted additional processing is performed including the final address pointer updates reloading the TCDn CITER field and a possible fetch of the next TCDn from memory as part of a scatter gather...

Page 280: ...eDMA basic data flow The eDMA transfers data based on a two deep nested flow The basic flow of a data transfer can be partitioned into three segments As shown in Figure 16 19 the first segment involve...

Page 281: ...data is temporarily stored in the data path module until it is gated onto the system bus during the destination write This source read destination write processing continues until the inner minor byt...

Page 282: ...he final address adjustments and reloading of the BITER field into the CITER Additionally assertion of an optional interrupt request occurs at this time as does a possible fetch of a new TCD from memo...

Page 283: ...yte TCD for each channel that may request service 5 Enable any hardware service requests via the EDMA_ERQRH and or EDMA_ERQRL registers 6 Request channel service by software setting the TCD START bit...

Page 284: ...catter gather operations if enabled Figure 16 22 shows how each DMA request initiates one minor loop transfer iteration without CPU intervention DMA arbitration can occur after each minor loop and one...

Page 285: ...ded in the EDMA_ESR If the error source is not removed before the next activation of the problem channel the error will be detected and recorded again DMA request Minor loop 3 Current major loop itera...

Page 286: ...Table 16 21 DMA request summary for eDMA DMA Request Channel Source Description DMA_MUX_CHCONFIG0_SOURCE 0 DMA_MUX CHCONFIG0 SOURCE DMA MUX channel 0 source DMA_MUX_CHCONFIG1_SOURCE 1 DMA_MUX CHCONFI...

Page 287: ...4 bytes for the destination The final source and destination addresses are adjusted to return to their beginning values TCD CITER TCD BITER 1 TCD NBYTES 16 TCD SADDR 0x1000 TCD SOFF 1 TCD SSIZE 0 TCD...

Page 288: ...s are enabled in the EDMA_ERQR channel service requests are initiated by the slave device ERQR should be set after TCD Note that TCD START 0 TCD CITER TCD BITER 2 TCD NBYTES 16 TCD SADDR 0x1000 TCD SO...

Page 289: ...1018 read_byte 0x1019 read_byte 0x101a read_byte 0x101b f write_word 0x2018 third iteration of the minor loop g read_byte 0x101c read_byte 0x101d read_byte 0x101e read_byte 0x101f h write_word 0x201c...

Page 290: ...TIVE 1 TCD DONE 0 channel is executing 3 TCD START 0 TCD ACTIVE 0 TCD DONE 0 channel has completed the minor loop and is idle or 4 TCD START 0 TCD ACTIVE 0 TCD DONE 1 channel has completed the major l...

Page 291: ...s equal or more exactly constantly rotating when round robin arbitration mode is selected The TCD ACTIVE bit for the preempted channel remains asserted throughout the preemption The preempted channel...

Page 292: ...nel linking Dynamic channel linking is the process of setting the TCD major e_link bit during channel execution This bit is read from the TCD local memory at the end of channel execution thus allowing...

Page 293: ...r s model but it would be unclear whether the actual scatter gather request was honored before the channel retired Two methods for this coherency model are shown in the following subsections Method 1...

Page 294: ...field with the scatter gather address 4 Write 1b to the TCD e_sg bit 5 Read back the 16 bit TCD control status field 6 Test the TCD e_sg request status and TCD major linkch value If e_sg 1b the dynami...

Page 295: ...1 DMA_MUX block diagram 17 2 Features The DMA_MUX has these major features 16 independently selectable eDMA channel routers Four channels with normal or periodic triggering capability 12 channels with...

Page 296: ...buffer becomes empty or a receive buffer becomes full periodically The period is configured in the registers of the Periodic Interrupt Timer PIT eDMA channels 0 3 may be used in all three modes but ch...

Page 297: ...eDMA Channel Enable ENBL enables the eDMA channel 0 eDMA channel is disabled This mode is primarily used during configuration of the DMA_MUX The eDMA has separate channel enables disables which should...

Page 298: ...SPI_3 RX DMA_MUX Source 8 9 DSPI 4 DSPI_4 TX DMA_MUX Source 9 10 DSPI 4 DSPI_4 RX DMA_MUX Source 10 11 DSPI 5 DSPI_5 TX DMA_MUX Source 11 12 DSPI 5 DSPI_5 RX DMA_MUX Source 12 13 DMA_MUX Source 13 14...

Page 299: ...X 1 LINFLEX1_TX DMA_MUX Source 36 37 DMA_MUX Source 37 38 DMA_MUX Source 38 39 DMA_MUX Source 39 40 DMA_MUX Source 40 41 DMA_MUX Source 41 42 DMA_MUX Source 42 43 DMA_MUX Source 43 44 DMA_MUX Source 4...

Page 300: ...ng functionality 17 7 1 eDMA channels with periodic triggering capability Besides the normal routing functionality the first four channels of the DMA_MUX provide a special periodic triggering capabili...

Page 301: ...hannel 0 3 block diagram The eDMA channel triggering capability allows the system to schedule regular eDMA transfers usually on the transmit side of certain peripherals without the intervention of the...

Page 302: ...example the transmit side of a DSPI is assigned to an eDMA channel with a trigger as described above Once set up the SPI will request eDMA transfers presumably from memory as long as its transmit buff...

Page 303: ...y enabled before use 17 8 2 Enabling and configuring sources 17 8 2 1 Enabling a source with periodic triggering The following describes how to enable a source with periodic triggering 1 Determine wit...

Page 304: ...CHCONFIG2 0x00 CHCONFIG2 0xC3 17 8 2 2 Enabling a source without periodic triggering The following describes how to enable a source without periodic triggering 1 Determine with which eDMA channel the...

Page 305: ...he ENBL and TRIG bits of the eDMA channel 3 Select the source to be routed to the eDMA channel Write to the corresponding CHCONFIG register ensuring that the ENBL and TRIG bits are set Example 17 3 Sw...

Page 306: ...Chapter 17 eDMA Channel Multiplexer DMA_MUX MPC5606BK Microcontroller Reference Manual Rev 2 306 Freescale Semiconductor This page is intentionally left blank...

Page 307: ...The INTC supports the priority ceiling protocol for coherent accesses By providing a modifiable priority mask the priority can be raised temporarily so that all tasks that share the resource cannot p...

Page 308: ...are 8 ECSM 1 eDMA 17 Software Watchdog SWT 1 STM 4 Flash SRAM ECC SEC DED 2 Real Time Counter RTC API 2 System Integration Unit Lite SIUL 3 WKPU 4 MC_ME 4 MC_RGM 1 FXOSC 1 SXOSC 1 PIT 8 ADC_0 2 ADC_1...

Page 309: ...Clear Interrupt Registers Flag Bits Priority Select Registers Peripheral Interrupt Requests Module Configuration Register Highest Priority 4 Priority Comparator Slave Interface for Reads Writes 1 Pus...

Page 310: ...on to all of them The INTC uses hardware vector mode for a given processor when the associated HVEN bit in the INTC_MCR is asserted The hardware vector enable signal to the associated processor is dri...

Page 311: ...supported provided that the access does not cross a register boundary These supported accesses include types and sizes of 8 bits aligned 16 bits misaligned 16 bits to the middle 2 bytes and aligned 3...

Page 312: ...29 30 31 R 0 0 0 0 0 0 0 0 0 0 VTES 0 0 0 0 HVEN W Reset 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 Figure 18 2 INTC Module Configuration Register INTC_MCR Table 18 3 INTC_MCR field descriptions Field Descripti...

Page 313: ...I field supporting the PCP Refer to Section 18 7 5 Priority ceiling protocol NOTE A store to modify the PRI field that closely precedes or follows an access to a shared resource can result in a non co...

Page 314: ...set 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 16 17 18 19 20 21 22 23 24 25 26 27 28 29 30 31 R VTBA 4 0 INTVEC 0 0 W Reset 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 Figure 18 4 INTC Interrupt Acknowledge Register INTC_I...

Page 315: ...tion 18 4 1 2 Hardware vector mode The values and size of data written to the INTC_EOIR are ignored The values and sizes written to this register neither update the INTC_EOIR contents or affect whethe...

Page 316: ...0 0 Figure 18 7 INTC Software Set Clear Interrupt Register 0 3 INTC_SSCIR 0 3 Offset 0x0024 Access User read write 0 1 2 3 4 5 6 7 8 9 10 11 12 13 14 15 R 0 0 0 0 0 0 0 CLR4 0 0 0 0 0 0 0 CLR5 W SET4...

Page 317: ...Registers INTC_PSR0_3 INTC_PSR232_233 Offset 0x0040 Access User read write 0 1 2 3 4 5 6 7 8 9 10 11 12 13 14 15 R 0 0 0 0 PRI0 0 0 0 0 PRI1 W Reset 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 16 17 18 19 20 21...

Page 318: ...C_PSR40_43 0x0068 INTC_PSR160_163 0x00E0 INTC_PSR44_47 0x006C INTC_PSR164_167 0x00E4 INTC_PSR48_51 0x0070 INTC_PSR168_171 0x00E8 INTC_PSR52_55 0x0074 INTC_PSR172_175 0x00EC INTC_PSR56_59 0x0078 INTC_P...

Page 319: ...ftware settable interrupt request Also the PRI value in the INTC_CPR will be updated with the corresponding PRIn value in INTC_PSRn Furthermore clearing the peripheral interrupt request s enable bit i...

Page 320: ...Bank 0 Stall Platform Flash Bank 1 Abort Platform Flash Bank 1 Stall ECSM 10 0x0828 4 Combined Error eDMA 11 0x082C 4 Channel 0 eDMA 12 0x0830 4 Channel 1 eDMA 13 0x0834 4 Channel 2 eDMA 14 0x0838 4...

Page 321: ...External IRQ_0 SIUL 42 0x08A8 4 SIU External IRQ_1 SIUL 43 0x08AC 4 SIU External IRQ_2 SIUL 44 0x08B0 4 Reserved 45 0x08B4 4 Reserved 46 0x08B8 4 WakeUp_IRQ_0 WKPU 47 0x08BC 4 WakeUp_IRQ_1 WKPU 48 0x0...

Page 322: ...C 4 FlexCAN_BUF_12_15 FlexCAN_0 72 0x0920 4 FlexCAN_BUF_16_31 FlexCAN_0 73 0x0924 4 FlexCAN_BUF_32_63 FlexCAN_0 74 0x0928 4 DSPI_SR TFUF DSPI_SR RFOF DSPI_0 75 0x092C 4 DSPI_SR EOQF DSPI_0 76 0x0930 4...

Page 323: ...1 0x0994 4 LINFlex_ERR LINFlex_1 102 0x0998 4 Reserved 103 0x099C 4 Reserved 104 0x09A0 4 Reserved 105 0x09A4 4 FlexCAN_ ERR_INT FlexCAN_2 106 0x09A8 4 FlexCAN_ESR_BOFF FlexCAN_Transmit_Warning FlexCA...

Page 324: ...5 PIT 130 0x0A08 4 PITimer Channel 6 PIT 131 0x0A0C 4 PITimer Channel 7 PIT 132 0x0A10 4 Reserved 133 0x0A14 4 Reserved 134 0x0A18 4 Reserved 135 0x0A1C 4 Reserved 136 0x0A20 4 Reserved 137 0x0A24 4 R...

Page 325: ...0A88 4 EMIOS_GFR F10 F11 eMIOS_1 163 0x0A8C 4 EMIOS_GFR F12 F13 eMIOS_1 164 0x0A90 4 EMIOS_GFR F14 F15 eMIOS_1 165 0x0A94 4 EMIOS_GFR F16 F17 eMIOS_1 166 0x0A98 4 EMIOS_GFR F18 F19 eMIOS_1 167 0x0A9C...

Page 326: ...eive_Warning FlexCAN_4 192 0x0B00 4 Reserved 193 0x0B04 4 FlexCAN_BUF_0_3 FlexCAN_4 194 0x0B08 4 FlexCAN_BUF_4_7 FlexCAN_4 195 0x0B0C 4 FlexCAN_BUF_8_11 FlexCAN_4 196 0x0B10 4 FlexCAN_BUF_12_15 FlexCA...

Page 327: ...I_SR TCF DSPI_4 215 0x0B5C 4 DSPI_SR RFDF DSPI_4 216 0x0B60 4 LINFlex_RXI LINFlex_6 217 0x0B64 4 LINFlex_TXI LINFlex_6 218 0x0B68 4 LINFlex_ERR LINFlex_6 219 0x0B6C 4 DSPI_SR TFUF DSPI_SR RFOF DSPI_5...

Page 328: ...errupt requests The peripheral interrupt request input ports at the boundary of the INTC block are assigned specific hardwired vectors within the INTC see Table 18 1 18 6 2 Priority management The ass...

Page 329: ...he new priority which will be written to PRI in INTC_CPR when the interrupt request to the processor is acknowledged Interrupt requests whose PRIn in INTC_PSRn are zero will not cause a preemption bec...

Page 330: ...nd of interrupt exception handler Before the interrupt exception handling completes INTC end of interrupt register INTC_EOIR must be written When written the associated LIFO is popped so the preempted...

Page 331: ...R is updated with the preempting peripheral or software settable interrupt request s vector when the interrupt request to the processor is asserted The INTVEC field retains that value until the next t...

Page 332: ...terrupt requests are negated An initialization sequence for allowing the peripheral and software settable interrupt requests to cause an interrupt request to the processor is interrupt_request_initial...

Page 333: ...rupt request mbar ensure store to clear flag bit has completed lis r3 INTC_EOIR ha form adjusted upper half of INTC_EOIR address li r4 0x0 form 0 to write to INTC_EOIR wrteei 0 disable processor recog...

Page 334: ...ierarchy The RTOS and all of the tasks under its control typically execute with PRI in INTC current priority register INTC_CPR having a value of 0 The RTOS will execute the tasks according to whatever...

Page 335: ...ity Table 18 11 Order of ISR execution example Step No Step description Code Executing at End of Step PRI in INTC_CPR at End of Step RTOS ISR1081 1 ISR108 executes for peripheral interrupt request 100...

Page 336: ...oherency A scenario can cause non coherent accesses to the shared resource For example ISR1 and ISR2 are both running on the same core and both share a resource ISR1 has a lower priority than ISR2 ISR...

Page 337: ...the PRIx value in the INTC Priority Select Registers INTC_PSR0_3 INTC_PSR232_233 which becomes the PRI value in INTC_CPR with the interrupt acknowledge The ISR however can have a portion that does not...

Page 338: ...ue in INTC_CPR within an ISR to below the ISR s corresponding PRI value in the INTC Priority Select Registers INTC_PSR0_3 INTC_PSR232_233 allows more preemptions than the LIFO depth can support Theref...

Page 339: ...heral interrupt request can be cleared at any time regardless of the peripheral interrupt request s PRIx value in INTC_PSRx_x 18 7 10 Examining LIFO contents In normal mode the user does not need to k...

Page 340: ...Chapter 18 Interrupt Controller INTC MPC5606BK Microcontroller Reference Manual Rev 2 340 Freescale Semiconductor This page is intentionally left blank...

Page 341: ...software and that it has a hard wired configuration 19 2 Block diagram Figure 19 1 shows a block diagram of the crossbar switch Figure 19 1 XBAR block diagram Table 19 1 gives the crossbar switch por...

Page 342: ...er ports Core e200z0 core instructions Core e200z0 core data eDMA Three slave ports Flash refer to Chapter 30 Flash Memory for information on accessing flash memory Internal SRAM Peripheral bridges 32...

Page 343: ...ort B Lower priority master also makes a request to the different slave port B In this case the lower priority master is granted bus ownership of slave port B after a cycle of arbitration assuming the...

Page 344: ...port A requesting master that does not own the slave port is granted access after a one clock delay 19 6 5 Priority assignment Each master port is assigned a fixed 3 bit priority level hard wired prio...

Page 345: ...iority level is lower than that of the master that currently has control of the slave port the new requesting master is forced to wait until the master that currently has control of the slave port is...

Page 346: ...Chapter 19 Crossbar Switch XBAR MPC5606BK Microcontroller Reference Manual Rev 2 346 Freescale Semiconductor This page is intentionally left blank...

Page 347: ...r event configuration Figure 20 1 provides a block diagram of the SIUL and its interfaces to other system components The module provides the capability to configure read and write to the device s gene...

Page 348: ...terrupt Interrupt Controller IPS Master Configuration Glitch Filter Pad Config IOMUXC Pad Cfg PCRs GPIO Functionality 149 1 149 1 149 1 24 2 3 MUX PADS 149 1 SIUL Module Interrupt Functionality Notes...

Page 349: ...iate configuration all pins in a port can be read or written to in parallel with a single R W access NOTE In order to use GPIO port functionality all pads in the port must be configured as GPIO rather...

Page 350: ...her I O pin functions Each GPIO input and output is separately controlled by an input GPDIn_n or output GPDOn_n register 20 4 1 2 External interrupt request input pins EIRQ 0 23 2 The EIRQ 0 23 pins a...

Page 351: ...dge Event Enable Register IREER on page 356 0x002C Interrupt Falling Edge Event Enable Register IFEER on page 357 0x0030 Interrupt Filter Enable Register IFER on page 358 0x0034 0x003F Reserved 0x0040...

Page 352: ...Interrupt Filter Maximum Counter Registers IFMC0 IFMC23 Note that only IFMC 0 15 can be protected Interrupt Filter Clock Prescaler Register IFCPR See Chapter 32 Register Protection for more details 0x...

Page 353: ...mber lower 16 bits Device part number of the MCU 0101_0110_0000_0001 128 KB 0101_0110_0000_0010 256 KB 0101_0110_0000_0011 320 384 KB 0101_0110_0000_0100 512 KB 0101_0110_0000_0101 768 KB 0101_0110_00...

Page 354: ...20 3 MCU ID Register 2 MIDR2 Table 20 4 MIDR2 field descriptions Field Description SF Manufacturer 0 Freescale 1 Reserved FLASH_SIZE_1 Coarse granularity for Flash memory size Total flash memory size...

Page 355: ...set 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 16 17 18 19 20 21 22 23 24 25 26 27 28 29 30 31 R EIF 15 0 1 W w1c Reset 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 Figure 20 4 Interrupt Status Flag Register ISR Table 20 5 I...

Page 356: ...0 0 0 0 0 0 0 0 0 0 0 0 0 0 16 17 18 19 20 21 22 23 24 25 26 27 28 29 30 31 R IRE 15 0 1 W Reset 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 Figure 20 5 Interrupt Request Enable Register IRER Table 20 6 IRER fie...

Page 357: ...e events Table 20 7 IREER field descriptions Field Description IREE x Enable rising edge events to cause the ISR EIF x bit to be set 0 Rising edge event is disabled 1 Rising edge event is enabled Offs...

Page 358: ...nfig Register PCR OBE is not required for functions other than GPIO For input pads Select the feature location from PSMI register Set the IBE bit in the appropriate PCR For normal GPIO not alternate f...

Page 359: ...Reset 0 01 1 SMC and PA 1 are 1 for JTAG pads 0 0 01 0 02 2 OBE is 1 for TDO 03 3 IBE and WPE are 1 for TCK TMS TDI FAB and ABS 0 0 0 0 0 0 03 14 4 WPS is 0 for input only pad with analog feature and...

Page 360: ...e 0 Output buffer of the pad is disabled when PA 1 0 00 1 Output buffer of the pad is enabled when PA 1 0 00 IBE Input Buffer Enable This bit enables the input buffer of the pad 0 Input buffer of the...

Page 361: ...0 16 17 18 19 20 21 22 23 24 25 26 27 28 29 30 31 R 0 0 0 0 PADSEL2 0 0 0 0 PADSEL3 W Reset 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 Figure 20 10 Pad Selection for Multiplexed Inputs Register PSMI0_3 Table 20...

Page 362: ...0A SCK_2 DSPI_2 00 PCR 46 01 PCR 78 2 10 PCR 105 2 PADSEL11 0x50B SIN_2 DSPI_2 00 PCR 44 01 PCR 76 PSMI12_15 PADSEL12 0x50C CS0_2 DSPI_2 00 PCR 47 01 PCR 79 2 10 PCR 82 2 11 PCR 104 2 PADSEL13 0x50D E...

Page 363: ...PCR 75 PADSEL26 0x51A E0UC 25 eMIOS_0 00 PCR 61 01 PCR 107 2 PADSEL27 0x51B E0UC 26 eMIOS_0 00 PCR 62 01 PCR 108 2 PSMI28_31 PADSEL28 0x51C E0UC 27 eMIOS_0 00 PCR 63 01 PCR 109 2 PADSEL29 0x51D SCL f...

Page 364: ...2A E0UC 30 eMIOS_0 00 PCR 16 01 PCR 18 10 PCR 130 3 PADSEL43 0x52B E0UC 31 eMIOS0 00 PCR 17 01 PCR 19 10 PCR 131 3 PSMI44_47 PADSEL44 0x52C E1UC 1 eMIOS_1 00 PCR 111 2 01 PCR 89 2 PADSEL45 0x52D E1UC...

Page 365: ...MI56_59 PADSEL56 0x538 E1UC 30 eMIOS_1Reserved 00 PCR 74 01 PCR 103 2 10 PCR 134 3 PADSEL57 0x539 E1UC 31 eMIOS_1Reserved 00 PCR 36 01 PCR 106 2 10 PCR 135 3 PADSEL58 0x53A LIN2RX LINFlex _2 00 PCR 41...

Page 366: ...read write 0 1 2 3 4 5 6 7 8 9 10 11 12 13 14 15 R 0 0 0 0 0 0 0 PDO 0 0 0 0 0 0 0 0 PDO 1 W Reset 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 16 17 18 19 20 21 22 23 24 25 26 27 28 29 30 31 R 0 0 0 0 0 0 0 PDO 2...

Page 367: ...aining the port GPIO pads Toggling several GPIO pins simultaneously can significantly increase current consumption CAUTION Caution must be taken to avoid exceeding maximum current thresholds when togg...

Page 368: ...a single pin within a port has IBE set then you can still read that pin using the parallel port register However this does mean you need to be very careful Reads of PGPDI registers are equivalent to...

Page 369: ...ach 32 bit MPGPDOx register is associated to only one port NOTE The MPGPDOx registers may only be accessed with 32 bit writes 8 bit or 16 bit writes will not modify any bits in the register and will c...

Page 370: ...nfigure the filter counter associated with each digital glitch filter NOTE For the pad transition to trigger an interrupt it must be steady for at least the filter period 0x0C9C MPGPDO7 MASK7 Port H M...

Page 371: ...eset 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 Figure 20 13 Interrupt Filter Maximum Counter Registers IFMC0 IFMC23 Table 20 20 IFMC field descriptions Field Description MAXCNTx Maximum Interrupt Filter Counter...

Page 372: ...Control of analog path switches Safe mode behavior configuration 20 6 2 General purpose input and output pads GPIO The SIUL manages as many as 149 GPIO pads organized as ports that can be accessed for...

Page 373: ...a write operation is performed to the data output register for a pad configured as an alternate function non GPIO this write will not be reflected by the pad value until reconfigured to GPIO The allo...

Page 374: ...igured The active EIRQ edge is controlled through the configuration of the registers IREER and IFEER Each external interrupt supports an individual flag in the Interrupt Status Flag Register ISR The b...

Page 375: ...the following capabilities Support for 8 program visible 128 bit 4 word region descriptors Each region descriptor defines a modulo 32 byte space aligned anywhere in memory Region sizes can vary from a...

Page 376: ...s masters processor cores support the traditional read write execute permissions with independent definitions for supervisor and user mode accesses Automatic hardware maintenance of the region descrip...

Page 377: ...ection functions are evaluated on a reference by reference basis using the addresses from the XBAR system bus port s Power dissipation is minimized when the MPU s global enable disable bit is cleared...

Page 378: ...FF Reserved 0x400 MPU Region Descriptor 0 MPU_RGD0 on page 382 0x410 MPU Region Descriptor 1 MPU_RGD1 on page 382 0x420 MPU Region Descriptor 2 MPU_RGD2 on page 382 0x430 MPU Region Descriptor 3 MPU_R...

Page 379: ...the presence of a captured error contained in the MPU_EARn and MPU_EDRn registers The individual bit is set when the hardware detects an error and records the faulting address and attributes It is cl...

Page 380: ...n the occurrence of each protection violation VLD Valid This bit provides a global enable disable for the MPU 0 The MPU is disabled 1 The MPU is enabled While the MPU is disabled all accesses from all...

Page 381: ...implements one bit per region descriptor and is an indication of the region descriptor hit logically ANDed with the access error indication The MPU performs a reference by reference evaluation to det...

Page 382: ...alid bit see Section 21 5 2 4 4 MPU Region Descriptor n Word 3 MPU_RGDn Word3 for more information EATTR Error Attributes This field records attribute information about the faulting reference The supp...

Page 383: ...reserved for data movement engines and their capabilities are limited to separate read and write permissions For these fields the bus master number refers to the logical master number defined as the...

Page 384: ...t entity is provided If only the access controls are being updated this operation should be performed by writing to MPU_RGDAACn Alternate Access Control n as stores to these locations do not affect th...

Page 385: ...mode The M3SM field is defined as 00 r w x read write and execute allowed 01 r x read and execute allowed but no write 10 r w read and write allowed but no execute 11 Same access controls as that def...

Page 386: ...g view of this 32 bit entity is provided If only the access controls are being updated this operation should be performed by writing to MPU_RGDAACn Alternate Access Control n as stores to these locati...

Page 387: ...0 0 0 0 0 0 Figure 21 8 MPU Region Descriptor Word 3 Register MPU_RGDn Word3 Table 21 9 MPU_RGDn Word3 field descriptions Field Description PID Process Identifier This field specifies that the optiona...

Page 388: ...or and the write is not performed M6RE Bus master 6 read enable If set this flag allows bus master 6 to perform read operations If cleared any attempted read by bus master 6 terminates with an access...

Page 389: ...supervisor mode The M2SM field is defined as 00 r w read and write allowed 01 r read allowed but no write 10 r w read and write allowed 11 Same access controls as that defined by M2UM for user mode M...

Page 390: ...eneralized block diagram showing the major functions included in this logic block 21 6 1 1 Access evaluation Hit determination To evaluate the region hit determination the MPU uses two magnitude compa...

Page 391: ...nates the bus cycle with an error and reports a protection error for three conditions If the access does not hit in any region descriptor a protection error is reported If the access hits in a single...

Page 392: ...loaded into a RGDn it would typically be performed using four 32 bit word writes As discussed in Section 21 5 2 4 4 MPU Region Descriptor n Word 3 MPU_RGDn Word3 the hardware assists in the maintenanc...

Page 393: ...generate a core exception whereas the DMA errors generate a MPU external interrupt It is important to highlight that in case of DMA access violations the core continues to run but if a core violation...

Page 394: ...Chapter 21 Memory Protection Unit MPU MPC5606BK Microcontroller Reference Manual Rev 2 394 Freescale Semiconductor This page is intentionally left blank...

Page 395: ...MPC5606BK Microcontroller Reference Manual Rev 2 Freescale Semiconductor 395 Communication modules...

Page 396: ...MPC5606BK Microcontroller Reference Manual Rev 2 396 Freescale Semiconductor This page is intentionally left blank...

Page 397: ...evice is capable of operating at higher baud rates up to a maximum of module clock 20 with reduced bus loading Actual baud rate can be less than the programmed baud rate and is dependent on the SCL ri...

Page 398: ...tional Serial Clock Line SCL of the module compatible with the I2 C Bus specification 22 2 2 SDA This is the bidirectional Serial Data line SDA of the module compatible with the I2 C Bus specification...

Page 399: ...as a slave note that it is not the address sent on the bus during the address transfer Table 22 1 I2C memory map Base address 0xFFE3_0000 Address offset Register Location 0x0 I2C Bus Address Register...

Page 400: ...the clock for bit rate selection The bit clock generator is implemented as a prescale divider The IBC bits are decoded to give the Tap and Prescale values as follows 7 6 select the prescaled shift re...

Page 401: ...22 5 All subsequent tap points are separated by 2IBC5 3 as shown in the tap2tap column in Table 22 5 The SCL Tap is used to generate the SCL period and the SDA Tap is used to determine the delay from...

Page 402: ...The SDA hold delay is equal to the CPU clock period multiplied by the SDA Hold value shown in Table 22 7 The equation used to generate the SDA Hold value from the IBFD bits is SDA Hold MUL scl2tap SD...

Page 403: ...45 16 104 21 46 53 17 128 21 58 65 18 80 9 38 41 19 96 9 46 49 1A 112 17 54 57 1B 128 17 62 65 1C 144 25 70 73 1D 160 25 78 81 1E 192 33 94 97 1F 240 33 118 121 20 160 17 78 81 21 192 17 94 97 22 224...

Page 404: ...D 320 50 156 162 5E 384 66 188 194 5F 480 66 236 242 60 320 28 156 162 61 384 28 188 194 62 448 32 220 226 63 512 32 252 258 64 576 36 284 290 65 640 36 316 322 66 768 40 380 386 67 960 40 476 482 68...

Page 405: ...4 9E 768 132 376 388 9F 960 132 472 484 A0 640 68 312 324 A1 768 68 376 388 A2 896 132 440 452 A3 1024 132 504 516 A4 1152 196 568 580 A5 1280 196 632 644 A6 1536 260 760 772 A7 1920 260 952 964 A8 12...

Page 406: ...ule are enabled An I2C Bus interrupt occurs provided the IBIF bit in the status register is also set 0 Interrupts from the I2 C Bus module are disabled Note that this does not clear any currently pend...

Page 407: ...tion section for more details 1 Enable the DMA TX RX request signals 0 Disable the DMA TX RX request signals Offset 0x3 Access Read write 7 6 5 4 3 2 1 0 R TCF IAAS IBB IBAL 0 SRW IBIF RXAK W w1c w1c...

Page 408: ...it SRW Slave Read Write When IAAS is set this bit indicates the value of the R W command bit of the calling address sent from the master This bit is only valid when the I Bus is in slave mode a compl...

Page 409: ...implemented so that the I2 C can request data transfers with minimal support from the CPU DMA mode is enabled by setting bit 1 in the Control Register The DMA interface is only valid when the I2C mod...

Page 410: ...n practice it will only be worthwhile using the DMA mode when there is a large number of data bytes to transfer per frame Two internal signals TX request and RX request are used to signal to a DMA con...

Page 411: ...transmission signals 22 5 1 1 START signal When the bus is free that is no master device is engaging the bus both SCL and SDA lines are at logical high a master may initiate communication by sending a...

Page 412: ...smit an address that is equal to its own slave address The I2C bus cannot be master and slave at the same time However if arbitration is lost during an address cycle the I2C bus will revert to slave m...

Page 413: ...to be connected on it If two or more masters try to control the bus at the same time a clock synchronization procedure determines the bus clock for which the low period is equal to the longest clock...

Page 414: ...bit rate of a transfer After the master has driven SCL low the slave can drive SCL low for the required period and then release it If the slave SCL low period is greater than the master SCL low perio...

Page 415: ...carried out as follows 1 Update the Frequency Divider Register IBFD and select the required division ratio to obtain SCL frequency from system clock 2 Update the I2 C Bus Address Register IBAD to defi...

Page 416: ...ncy This bit may not conclusively provide an indication of a transfer complete situation It is recommended that transfer complete situations are detected using the IBIF flag Software may service the I...

Page 417: ...gress state 8 Wait until IBSR IBIF bit gets set To find its source check if TCF 1 i e reception is complete IBSR IBB 0 that is bus has transitioned from Busy to Idle state Ignore Arbitration Loss IBAL...

Page 418: ...ead as set is from the interrupt at the end of the address cycle where an address match occurred Interrupts resulting from subsequent data transfers will have IAAS cleared A data transfer may now be i...

Page 419: ...IBDR Switch To Rx Mode Dummy Read From IBDR Generate Stop Signal Read Data From IBDR And Store Set TXAK 1 Generate Stop Signal 2nd Last Byte To Be Read Last Byte To Be Read Arbitration Lost Clear IBAL...

Page 420: ...Chapter 22 Inter Integrated Circuit Bus Controller Module I2 C MPC5606BK Microcontroller Reference Manual Rev 2 420 Freescale Semiconductor This page is intentionally left blank...

Page 421: ...us message handling Classic and enhanced checksum calculation and check Single 8 byte buffer for transmission reception Extended frame mode for In Application Programming IAP purposes Wake up event on...

Page 422: ...Flex handles the LIN messages autonomously In Master mode once the software has triggered the header transmission LINFlex does not request any software intervention until the next header transmission...

Page 423: ...to the same value as programmed in the Mantissa LINIBRR and Fraction LINFBRR registers LIN master node LIN slave node 1 LIN slave node n LIN LIN LIN Rx Tx LIN Transceiver LINFlex Controller MCU LIN B...

Page 424: ...nters are updated with the new value of the baud registers after a write to LINIBRR Hence the baud register value must not be changed during a transaction The LINFBRR containing the Fraction bits must...

Page 425: ...52 1 0 04 57600 57605 8 69 7 0 01 57554 17 6 0 08 115200 115108 34 12 0 08 115108 8 11 0 08 230400 230216 17 6 0 08 231884 4 5 0 644 460800 460432 8 11 0 08 457143 2 3 0 794 921600 927536 4 5 0 644 9...

Page 426: ...lex has a low power mode called Sleep mode To enter Sleep mode software sets the SLEEP bit in the LINCR1 In this mode the LINFlex clock is stopped Consequently the LINFlex will not update the status b...

Page 427: ...LINTX pin 23 6 2 Self Test mode LINFlex can be put in Self Test mode by setting the LBKM and SFTM bits in the LINCR This mode can be used for a Hot Self Test meaning the LINFlex can be tested as in Lo...

Page 428: ...ffer data register LSB BDRL 1 on page 446 0x003C Buffer data register MSB BDRM 2 on page 447 0x0040 Identifier filter enable register IFER on page 448 0x0044 Identifier filter match index IFMI on page...

Page 429: ...his bit disables the checksum calculation see Table 23 4 0 Checksum calculation is done by hardware When this bit is 0 the LINCFR is read only 1 Checksum calculation is disabled When this bit is set t...

Page 430: ...is read only in Normal or Sleep mode LBKM Loop Back Mode This bit controls the Loop Back mode For more details see Section 23 6 1 Loop Back mode 0 Loop Back mode disable 1 Loop Back mode enable Note...

Page 431: ...Programmed in LINCFR by bits CF 0 7 0 0 Read only Hardware calculated Table 23 5 LIN master break length selection MBL Length 0000 10 bit 0001 11 bit 0010 12 bit 0011 13 bit 0100 14 bit 0101 15 bit 0...

Page 432: ...r UARTSR is set 1 Interrupt generated when OCF bit in LINESR or UARTSR is set BEIE Bit Error Interrupt Enable 0 No interrupt when BEF bit in LINESR is set 1 Interrupt generated when BEF bit in LINESR...

Page 433: ...pleted 1 Interrupt generated when data received flag DRF in LINSR or UARTSR is set DTIE Data Transmitted Interrupt Enable 0 No interrupt when data transmission is completed 1 Interrupt generated when...

Page 434: ...de Break transmission has been completed Break Delimiter transmission is ongoing 0101 Synch Field In Slave mode a valid Break Delimiter has been detected recessive state for at least one bit time Rece...

Page 435: ...fer has been filled again in order to start transmission This bit is reset by hardware in Initialization mode DRF Data Reception Completed Flag This bit is set by hardware and indicates the data recep...

Page 436: ...INFlex moves to Idle state If LTOM bit in LINTCSR is set then OCF is cleared by hardware in Initialization mode If LTOM bit is cleared then OCF maintains its status whatever the mode is BEF Bit Error...

Page 437: ...ared by software Offset 0x0010 Access User read write 0 1 2 3 4 5 6 7 8 9 10 11 12 13 14 15 R 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 W Reset 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 16 17 18 19 20 21 22 23 24 25 26 2...

Page 438: ...t check disable 1 Parity transmit check enable This bit can be programmed in Initialization mode only when the UART bit is set WL Word Length in UART mode 0 7 bit data parity bit 1 8 bit data or 9 bit...

Page 439: ...e No interrupt is generated if this error occurs 0 No parity error 1 Parity error PE0 Parity Error Flag Rx0 This bit indicates if there is a parity error in the corresponding received byte Rx0 See Sec...

Page 440: ...set by hardware in Initialization mode An interrupt is generated if DTIE bit in LINIER is set NF Noise Flag This bit is set by hardware when noise is detected on a received character This bit is clear...

Page 441: ...field indicates the LIN timeout counter value Offset 0x001C Access User read write 0 1 2 3 4 5 6 7 8 9 10 11 12 13 14 15 R 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 W Reset 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 16 1...

Page 442: ...lue This field contains the response timeout duration in bit time for 1 byte The reset value is 0xE 14 corresponding to TResponse_Maximum 1 4 TResponse_Nominal HTO Header timeout value This field cont...

Page 443: ...set 0x0028 Access User read write 0 1 2 3 4 5 6 7 8 9 10 11 12 13 14 15 R 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 W Reset 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 16 17 18 19 20 21 22 23 24 25 26 27 28 29 30 31 R 0 0...

Page 444: ...FR field descriptions Field Description CF Checksum bits When LINCR1 CCD 0 this field is read only When LINCR1 CCD 1 this field is read write See Table 23 4 Offset 0x0030 Access User read write 0 1 2...

Page 445: ...ta Transmission Request Set by software in Slave mode to request the transmission of the LIN Data field stored in the Buffer data register This bit can be set only when HRF bit in LINSR is set Cleared...

Page 446: ...ecksum applied on the current message 0 Enhanced Checksum covering Identifier and Data fields This is compatible with LIN specification 2 0 and higher 1 Classic Checksum covering Data fields only This...

Page 447: ...14 15 R DATA7 DATA6 W Reset 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 16 17 18 19 20 21 22 23 24 25 26 27 28 29 30 31 R DATA5 DATA4 W Reset 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 Figure 23 21 Buffer data register MSB...

Page 448: ...ter activation see Table 23 24 0 Filters 2n and 2n 1 are deactivated 1 Filters 2n and 2n 1 are activated This field can be set cleared in Initialization mode only Table 23 24 IFER FACT configuration B...

Page 449: ...16 17 18 19 20 21 22 23 24 25 26 27 28 29 30 31 R 0 0 0 0 0 0 0 0 0 0 0 IFMI 0 4 W Reset 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 Figure 23 23 Identifier filter match index IFMI Table 23 25 IFMI field descript...

Page 450: ...uration Bit Value Result IFM 0 0 Filters 0 and 1 are in identifier list mode 1 Filters 0 and 1 are in mask mode filter 1 is the mask for the filter 0 IFM 1 0 Filters 2 and 3 are in identifier list mod...

Page 451: ...25 Identifier filter control register IFCR2n Table 23 28 IFCR2n field descriptions Field Description DFL Data Field Length This field defines the number of data bytes in the response part of the frame...

Page 452: ...ble 23 29 IFCR2n 1 field descriptions Field Description DFL Data Field Length This field defines the number of data bytes in the response part of the frame DFL Number of data bytes 1 DIR Direction Thi...

Page 453: ...even parity is set if the modulo 2 sum of the 7 data bits is 1 An odd parity is cleared in this case Figure 23 27 UART mode 8 bit data frame 9 bit frames The 9th bit is a parity bit Even Odd Parity c...

Page 454: ...ng a reception then the current reception is completed and no further reception can be invoked until RXEN is set If a parity error occurs during reception of any byte then the corresponding PEx bit in...

Page 455: ...ve task of a node To transmit a header with LINFlex the application must set up the identifier and the data field length and configure the message direction and checksum type in the BIDR before reques...

Page 456: ...have been received The application has to read the buffer BDR before resetting the DBFF bit Once the last data byte or the checksum byte has been received the DRF flag is set 23 8 2 1 4 Data discard T...

Page 457: ...R2 DTRQ bit One or several identifier filters can be configured for transmission by setting the IFCRx DIR bit and activated by setting one or several bits in the IFER When at least one identifier filt...

Page 458: ...s the pointer that points to the right data array in the SRAM area and copy this data from the BDAR to the SRAM see Figure 23 30 Using a filter avoids the software reading the ID value in the BIDR and...

Page 459: ...ocol 23 8 2 2 8 Overrun Once the message buffer is full the next valid message reception leads to an overrun and a message is lost The hardware sets the BOF bit in the LINSR to signal the overrun cond...

Page 460: ...ration register organization 23 8 2 3 2 Identifier filter mode configuration The identifier filters are configured in the IFCRx registers To configure an identifier filter the filter must first be dea...

Page 461: ...by the LASE bit In this mode LINFlex adjusts the fractional baud rate generator after each Synch Field reception Table 23 31 Filter to interrupt vector correlation Number of active filters Number of...

Page 462: ...y software at LINIBRR and LINFBRR addresses LFDIV_MEAS results of the Field Synch measurement LFDIV used to generate the local baud rate On transition to idle break or break delimiter state due to any...

Page 463: ...d frame timeout Depending on the LIN mode selected by the LINCR1 MME bit the 8 bit timeout counter will behave differently LIN timeout mode must not be enabled during LIN extended frames transmission...

Page 464: ...OC2 is updated with the value of OCFrame OCFrame CNT HTO RTO 9 frame timeout value for an 8 byte frame The TOCE bit is set On the start bit of the first response data byte and if no error occurred du...

Page 465: ...RXI or TXI depending on the value of identifier received Data Transmitted interrupt DTF DTIE TXI Data Received interrupt DRF DRIE RXI Data Buffer Empty interrupt DBEF DBEIE TXI Data Buffer Full inter...

Page 466: ...Chapter 23 LIN Controller LINFlex MPC5606BK Microcontroller Reference Manual Rev 2 466 Freescale Semiconductor This page is intentionally left blank...

Page 467: ...system robustness minimize CPU load and allow slave node resynchronization Figure 24 1 shows the LINFlexD block diagram Figure 24 1 LINFlexD block diagram 24 2 Main features The LINFlexD controller c...

Page 468: ...tion and check Single 8 byte buffer for transmission reception Extended frame mode for In application Programming purposes Wake up event on dominant bit detection True LIN field state machine Advanced...

Page 469: ...slave task all other nodes contain a slave task only The master node decides when and which frame shall be transferred on the bus The slave task provides the data to be transported by the frame Figure...

Page 470: ...response 24 3 3 1 Break field The break field shown in Figure 24 4 is used to signal the beginning of a new frame It is always generated by the master and consists of At least 13 dominant bits includ...

Page 471: ...igure 24 6 The LSB of the data is sent first and the MSB last The start bit is encoded as a dominant bit and the stop bit is encoded as a recessive bit Figure 24 6 Structure of the data field 24 3 4 2...

Page 472: ...has triggered the header transmission LINFlexD does not request any software that is application intervention until the next header transmission request in transmission mode or until the checksum rec...

Page 473: ...Slave mode with automatic resynchronization UART mode Test modes Loop Back mode Self Test mode These modes are discussed in detail in subsequent sections 24 6 Controller level operating modes 24 6 1...

Page 474: ...up is enabled LINCR1 AWUM is set and LINFlexD detects LIN bus activity that is if a wakeup pulse of 150 s is detected on the LIN bus On LIN bus activity detection hardware automatically performs the...

Page 475: ...INFlexD is able to detect and handle LIN communication errors A code stored in the LIN error status register LINESR signals the errors to the software Table 24 1 lists the errors detected in Master mo...

Page 476: ...c TX interrupt is generated Typically the software has to copy the data from RAM locations to the BDRL and BDRM registers To copy the data to the right location the software has to identify the data b...

Page 477: ...RAM see Figure 24 10 Using a filter avoids the software reading the ID value in the BIDR register and configuring the direction the data field length and the checksum type in the BIDR register If LINF...

Page 478: ...est message is always available to the software If the buffer lock function is enabled LINCR1 RBLM set the most recent message is discarded and the previous message is available in the buffer 24 7 3 S...

Page 479: ...ter a maximum of 16 identifiers In order to be able to handle more identifiers the filters can be configured to operate as masks Table 24 3 describes the two available filter submodes The bit mapping...

Page 480: ...ing this filter generate a TX interrupt If at least one active filter is configured as RX all received identifiers matching this filter generate an RX interrupt If no active filter is configured as RX...

Page 481: ...od When automatic resynchronization is enabled after each LIN break the time duration between five falling edges on RDI is sampled on as shown in Figure 24 11 Then the LFDIV value and its associated L...

Page 482: ...D1 14 84 LHE is set If D1 14 06 LHE is not set If 14 06 D1 14 84 LHE can be either set or reset depending on the dephasing between the signal on LINFlexD_RX pin the fipg_clock_lin clock The second ch...

Page 483: ...n be used for a Hot Self Test meaning the LINFlexD can be tested as in Loop Back mode but without affecting a running LIN system connected to the LINTX and LINRX pins In this mode the LINRX pin is dis...

Page 484: ...3 16 bit data frame The 16 bit UART data frame is shown in Figure 24 16 The 16th bit can be a data or a parity bit Parity even odd 0 or 1 can be selected by the UARTCR PC field Parity 0 forces a zero...

Page 485: ...ed is equal to the value configured by the UARTCR TDFLTFC field see Table 24 16 The Transmit buffer size is as follows 4 bytes when UARTCR WL1 0 2 half words when UARTCR WL1 1 Therefore the maximum tr...

Page 486: ...M Table 24 6 BDRL access in UART mode Access Mode1 1 As specified by UARTCR TFBM Word length2 2 As specified by the WL1 and WL0 bits of the UARTCR register In UART FIFO mode UARTCR TFBM 1 any read ope...

Page 487: ...O Byte Half word IPS transfer error Write Half word2 3 FIFO Byte Half word IPS transfer error Write Word FIFO Byte Half word IPS transfer error Read Byte4 5 6 7 BUFFER Byte Half word OK Read Half word...

Page 488: ...ted This interrupt is helpful in identifying which byte has the framing error since there is only one register bit for framing errors A new byte has been received but the last received frame has not b...

Page 489: ...oftware request by clearing the SLEEP bit of the LINCR register 1 The Sleep mode is exited automatically by hardware on RX dominant state detection The SLEEP bit of the LINCR register is cleared by ha...

Page 490: ...Mode Request This bit is set by software to request LINFlexD to enter Sleep mode This bit is cleared by software to exit Sleep mode or by hardware if the AWUM bit in LINCR1 and the WUF bit in LINSR ar...

Page 491: ...0 0 0 0 0 0 0 0 0 0 0 0 W Reset 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 16 17 18 19 20 21 22 23 24 25 26 27 28 29 30 31 R SZIE OCIE BEIE CEIE HEIE 0 0 FEIE BOIE LSIE WUIE DBFIE DBEIETOIE DRIE DTIE HRIE W w1c...

Page 492: ...reset when writing 1111 into the LIN state bits in the LINSR register WUIE Wake up Interrupt Enable 0 No interrupt when WUF bit in LINSR or UARTSR is set 1 Interrupt generated when WUF bit in LINSR or...

Page 493: ...8 Access User read write 0 1 2 3 4 5 6 7 8 9 10 11 12 13 14 15 R 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 W Reset 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 16 17 18 19 20 21 22 23 24 25 26 27 28 29 30 31 R LINS 0 0 RMB...

Page 494: ...ongoing 0101 Synch Field In Slave mode a valid Break Delimiter has been detected recessive state for at least one bit time Receiving Synch Field In Master mode Synch Field transmission is ongoing 0110...

Page 495: ...ission This bit is reset by hardware in Initialization mode DRF Data Reception Completed Flag This bit is set by hardware and indicates the data reception is completed This bit must be cleared by soft...

Page 496: ...2 0 7 in LINOCR If this bit is set and IOT bit in LINTCSR is set LINFlexD moves to Idle state If LTOM bit in LINTCSR register is set then OCF is reset by hardware in Initialization mode If LTOM bit is...

Page 497: ...re when a new data byte is received and the buffer full flag is not cleared If RBLM in LINCR1 is set then the new byte received is discarded If RBLM is reset then the new byte overwrites the buffer It...

Page 498: ...values are reserved This field is meaningful and can be programmed only when the UART bit is set RDFLRFC Receiver data field length Rx FIFO counter This field has one of two functions depending on the...

Page 499: ...ty sent is even 01 Parity sent is odd 10 A logical 0 is always transmitted checked as parity bit 11 A logical 1 is always transmitted checked as parity bit This field can be programmed in initializati...

Page 500: ...Compare Flag 0 No output compare event occurred 1 The content of the counter has matched the content of OC1 0 7 or OC2 0 7 in LINOCR An interrupt is generated if the OCIE bit in LINIER register is set...

Page 501: ...e of UARTCTO becomes equal to the preset value of the timeout UARTPTO register setting This field should be cleared by software The GCR SR field should be used to reset the receiver FSM to idle state...

Page 502: ...ption LTOM LIN timeout mode 0 LIN timeout mode header response and frame timeout detection 1 Output compare mode This bit can be set cleared in Initialization mode only IOT Idle on Timeout 0 LIN state...

Page 503: ...0 0 0 0 0 0 0 0 0 0 0 16 17 18 19 20 21 22 23 24 25 26 27 28 29 30 31 R OC21 OC11 W w1c1 w1c1 Reset 1 1 1 1 1 1 1 1 1 1 1 1 1 1 1 1 1 If LINTCSR LTOM 0 these fields are read only Figure 24 25 LIN outp...

Page 504: ...ter mode 2 Resets to 0 in Slave mode and to 1 in Master mode 3 HTO field can only be written in slave mode LINCR1 MME 0 Figure 24 26 LIN timeout control register LINTOCR Table 24 20 LINTOCR field desc...

Page 505: ...Initialization mode LINCR1 INIT 1 Figure 24 27 LIN timeout control register LINTOCR Table 24 21 LINFBRR field descriptions Field Description DIV_F Fraction bits of LFDIV The 4 fraction bits define th...

Page 506: ...aud rate selection DIV_M Mantissa 0x0 LIN clock disabled 0x1 1 0xFFFFE 1048574 0xFFFFF 1048575 Offset 0x2C Access User read write 0 1 2 3 4 5 6 7 8 9 10 11 12 13 14 15 R 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0...

Page 507: ...tifier Parity error reset LIN state machine This bit can be set cleared in Initialization mode only LINCR1 INIT 1 WURQ Wake up Generation Request Setting this bit generates a wake up pulse It is reset...

Page 508: ...e request has been completed or aborted This bit has no effect in UART mode Offset 0x34 Access User read write 0 1 2 3 4 5 6 7 8 9 10 11 12 13 14 15 R 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 W Reset 0 0 0 0 0...

Page 509: ...entifier Identifier part of the identifier field without the identifier parity Offset 0x38 Access User read write 0 1 2 3 4 5 6 7 8 9 10 11 12 13 14 15 R DATA3 DATA2 W Reset 0 0 0 0 0 0 0 0 0 0 0 0 0...

Page 510: ...TA6 W Reset 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 16 17 18 19 20 21 22 23 24 25 26 27 28 29 30 31 R DATA5 DATA4 W Reset 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 Figure 24 33 Buffer data register most significant BDR...

Page 511: ...iptions Field Description FACT Filter activation see Table 24 30 The software sets the bit FACT x to activate the filters x in identifier list mode In identifier mask mode bits FACT 2n 1 have no effec...

Page 512: ...1 2 3 4 5 6 7 8 9 10 11 12 13 14 15 R 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 W Reset 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 16 17 18 19 20 21 22 23 24 25 26 27 28 29 30 31 Reset 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 Figu...

Page 513: ...0 0 0 0 0 0 W Reset 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 16 17 18 19 20 21 22 23 24 25 26 27 28 29 30 31 Reset 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 Figure 24 36 Identifier filter mode register IFMR Table 24 32...

Page 514: ...de LINCR1 INIT 1 Figure 24 37 Identifier filter control registers IFCR0 IFCR15 Table 24 34 IFCR field descriptions Field Description DFL Data Field Length This field defines the number of data bytes i...

Page 515: ...st bit transmitted is mapped on the MSB bit BDR 7 BDR 15 BDR 23 BDR 31 RDFBM Received data first bit MSB This field controls the first bit of received data payload only as MSB LSB in both UART and LIN...

Page 516: ...Starts at 0 and counts upward Is clocked with the baud rate clock prescaled by a hard wired scaling factor of 16 Is automatically enabled when UARTCR RXEN 1 SR Soft reset If the software writes a 1 to...

Page 517: ...out register UARTCTO Table 24 37 UARTCTO field descriptions Field Description CTO Current value of the timeout counter This field is reset whenever one of the following occurs A new value is written t...

Page 518: ...mory access eDMA controller see the description of that controller for details on its operation and the transfer control descriptors TCDs referenced in this section Table 24 38 DMATXE field descriptio...

Page 519: ...n the master node Slave to Slave transmission of the header The register settings for the LINCR2 and BIDR registers for each class of LIN frame are shown in Table 24 40 Table 24 40 Register settings m...

Page 520: ...shown in Figure 24 44 The DMA TX FSM will move to IDLE state immediately at next clock edge if DMATXE 0 0 Slave to Master DDRQ 0 DTRQ 0 HTRQ 0 DFL payload size ID address CCS checksum DIR 0 RX Slave...

Page 521: ...e allowed Enables DMA TX channel request DMAERQH DMAERQL DTF DRF LIN idle DBEF DMA_TEN Token_DMA_RX True DMA TX transfer Req Ack minor major loop from RAM area to LINFlex registers DMA TX transfer is...

Page 522: ...the major loop BITER 14 0 1 Single iteration for the major loop NBYTES 31 0 4 4 0 4 8 N Data buffer is stuffed with dummy bytes if the length is not word aligned LINCR2 BIDR BDRL BDRM SADDR 31 0 RAM...

Page 523: ...The DMA RX FSM will move to IDLE state immediately at next clock edge if DMARXE 0 0 Figure 24 46 FSM to control the DMA RX interface master node The TCD settings word transfer are shown in Table 24 42...

Page 524: ...tion CITER 14 0 1 Single iteration for the major loop BITER 14 0 1 Single iteration for the major loop NBYTES 31 0 4 4 8 N Data buffer is stuffed with dummy bytes if the length is not word aligned BID...

Page 525: ...of the LINCR2 IFER IFMR and IFCR registers are shown in Table 24 43 The concept FSM to control the DMA Tx interface is shown in Figure 24 48 DMA TX FSM will move to idle state if DMATXE x 0 where x IF...

Page 526: ...0 TCD settings based on half word or byte transfer are allowed Enables DMA TX channel filter request DMAERQH DMAERQL DTF DRF DBEF HRF IFMI 0 DMA_TEN True DMA TX transfer Req Ack from RAM area to LINF...

Page 527: ...e iteration for the major loop BITER 14 0 1 Single iteration for the major loop NBYTES 31 0 4 8 N Data buffer is stuffed with dummy bytes if the length is not word aligned BDRL BDRM SADDR 31 0 RAM add...

Page 528: ...the LINCR2 IFER IFMR and IFCR registers are given in Table 24 45 The concept FSM to control the DMA Rx interface is shown in Figure 24 50 DMA RX FSM will move to idle state if DMARXE x 0 where x IFMI...

Page 529: ...Value Description CITER 14 0 1 Single iteration for the major loop BITER 14 0 1 Single iteration for the major loop NBYTES 31 0 4 4 8 N Data buffer is stuffed with dummy bytes if the length is not wor...

Page 530: ...from the RAM to the FIFO Use low priority DMA channels Support the UART baud rate 2 Mb s without underrun events The Tx FIFO size is SOFF 15 0 4 Word increment SSIZE 2 0 2 Word transfer SLAST 31 0 N D...

Page 531: ...FSM will move to idle state if DMATXE 0 0 Figure 24 52 FSM to control the DMA TX interface UART node The TCD settings typical case are shown in Table 24 47 All other TCD fields 0 The minor loop transf...

Page 532: ...ajor loop NBYTES 31 0 1 2 Minor loop transfer 1 or 2 bytes SADDR 31 0 RAM address SOFF 15 0 1 2 Byte half word increment SSIZE 2 0 0 1 Byte half word transfer SLAST 31 0 M M 2 DADDR 31 0 BDRL address...

Page 533: ...e low priority DMA channels Support high UART baud rate at least 2 Mb s without overrun events The Rx FIFO size is 4 bytes in 8 bit data format 2 half words in 16 bit data format This is sufficient be...

Page 534: ...fields 0 The minor loop transfers a single byte half word as soon an entry is available in the Rx FIFO A new software reset bit is RFE DMA_REN True False RFE UART RX buffer FIFO mode TIMEOUT config E...

Page 535: ...node Once a DMA transfer is finished the CPU can handle subsequent accesses Error management must be always executed via CPU enabling the related error interrupt sources The DMA capability does not p...

Page 536: ...Field OC1 checks THeader and TResponse and field OC2 checks TFrame refer to Figure 24 55 Header and response timeout When LINFlexD moves from Break delimiter state to Synch Field state refer to Sectio...

Page 537: ...OCResponse CNT RTO 9 response timeout value for an 8 byte frame Once the first response byte is received OC1 and OC2 are automatically updated to check TResponse and TFrame according to RTO tolerance...

Page 538: ...RR Framing Error interrupt FEF FEIE ERR Header Error interrupt HEF HEIE ERR Checksum Error interrupt CEF CEIE ERR Bit Error interrupt BEF BEIE ERR Output Compare interrupt OCF OCIE ERR Stuck at Zero i...

Page 539: ...tissa LINIBRR and Fraction LINFBRR registers LFDIV is an unsigned fixed point number The 20 bit mantissa is coded in the LINIBRR register and the fraction is coded in the LINFBRR register The followin...

Page 540: ...ters after a write to LINIBRR Hence the Baud Register value must not be changed during a transaction The LINFBRR containing the Fraction bits must be programmed before LINIBRR NOTE LFDIV must be great...

Page 541: ...ming consideration slave node transmitter no filters Header Data RX Checksum RX Configure ID DFL Set HTRQ RXI Interrupt DRF set DIR 0 and DDRQ 0 Header Data TX Configure ID DFL Data buffer Set HTRQ DI...

Page 542: ...e at least one TX filter BF is reset ID matches filter Header Data RX Checksum RX RX Interrupt DRF set Configure CCS DIR DFL HRF set RX Interrupt DDRQ 0 Header DDRQ 1 HRF set RX Interrupt Header Data...

Page 543: ...ure 24 68 Programming consideration slave node TX filter BF is set Header Data RX Checksum RX RXI Interrupt DRF set IFMI ID matched 1 Header ID not matching any filter Header Data TX Checksum TX TX In...

Page 544: ...DDRQ 0 Header Data transmit Checksum transmit Transmit interrupt DTF set HRF set Receive interrupt Set DTRQ Configure CCS DIR DFL data buffers ID is transmit Header Data transmit Checksum transmit Tra...

Page 545: ...ansmit 8 bytes transmit Checksum transmit Transmit interrupt DTF set Configure DIR DFL HRF set Receive interrupt ID not matched DBEF set Refill buffer Reset DBEF CCS DTRQ 1 Header 8 bytes receive 8 by...

Page 546: ...6BK Microcontroller Reference Manual Rev 2 546 Freescale Semiconductor 24 13 5 UART mode Figure 24 75 Programming consideration UART mode Data receive transmit DTF DRF is set Transmit receive interrup...

Page 547: ...Chapter 24 LIN Controller LINFlexD MPC5606BK Microcontroller Reference Manual Rev 2 Freescale Semiconductor 547 This page is intentionally left blank...

Page 548: ...Chapter 24 LIN Controller LINFlexD MPC5606BK Microcontroller Reference Manual Rev 2 548 Freescale Semiconductor...

Page 549: ...ive state Modes of operation Four functional modes Normal User and Supervisor Freeze Listen Only and Loop Back One low power mode Disable mode 1056 bytes 64 MBs of RAM used for MB storage 256 bytes 64...

Page 550: ...are stored in an embedded RAM dedicated to the FlexCAN module The CAN Protocol Interface CPI submodule manages the serial communication on the CAN bus requesting RAM access for receiving and transmitt...

Page 551: ...featured Rx FIFO with storage capacity for 6 frames and internal pointer handling Powerful Rx FIFO ID filtering capable of matching incoming IDs against either 8 extended 16 standard or 32 partial 8 b...

Page 552: ...hen the LPB bit in CTRL is asserted In this mode FlexCAN performs an internal loop back that can be used for self test operation The bit stream output of the transmitter is internally fed back to the...

Page 553: ...The complete memory map for a FlexCAN module with 64 MBs capability is shown in Table 25 2 All registers except for the MCR can be configured to have either supervisor or unrestricted access by progr...

Page 554: ...IMER on page 564 0x000C Reserved 0x0010 Rx Global Mask RXGMASK on page 565 0x0014 Rx Buffer 14 Mask RX14MASK on page 567 0x0018 Rx Buffer 15 Mask RX15MASK on page 567 0x001C Error Counter Register ECR...

Page 555: ...nformation SRR Substitute Remote Request Fixed recessive bit used only in extended format It must be set to 1 by the user for transmission Tx Buffers and will be stored with the value received on the...

Page 556: ...ificant bits 3 to 13 are used for frame identification in both receive and transmit cases The 18 least significant bits are ignored In Extended Frame format all bits are used for frame identification...

Page 557: ...in MCR is asserted MB does not participate in the arbitration process 0 1100 1000 Transmit data frame unconditionally once After transmission the MB automatically returns to the INACTIVE state 1 1100...

Page 558: ...le that specifies filtering criteria for accepting frames into the FIFO Figure 25 4 shows the three different formats that the elements of the ID table can assume depending on the IDAM field of the MC...

Page 559: ...they match the target ID 0 Remote Frames are rejected and data frames can be accepted 1 Remote Frames can be accepted and data frames are rejected EXT Extended Frame Specifies whether extended or sta...

Page 560: ...shuts down the clocks to the CAN Protocol Interface and Message Buffer Management submodules This is the only bit in MCR not affected by soft reset See Section 25 5 10 2 Module Disable mode for more...

Page 561: ...The SOFT_RST bit remains asserted while reset is pending and is automatically negated when reset completes Therefore software can poll this bit to know when the soft reset has completed Soft reset can...

Page 562: ...ion This bit is provided to support Backwards Compatibility with previous FlexCAN versions On this device FlexCAN supports individual Rx ID masking using RXIMR0 63 Setting this bit enables individual...

Page 563: ...elements of the table are configured at the same time by this field they are all the same format See Section 25 4 3 Rx FIFO structure This bit must be written in Freeze mode only MAXMB Maximum Number...

Page 564: ...For more information refer to Section 25 5 9 4 Protocol timing This bit must be written in Freeze mode only Sclock frequency CPI clock frequency PRESDIV 1 RJW Resync Jump Width This 2 bit field defin...

Page 565: ...ssage as a message received from a remote node In this mode FlexCAN ignores the bit sent during the ACK slot in the CAN frame acknowledge field generating an internal acknowledge bit to ensure proper...

Page 566: ...eans to synchronize multiple FlexCAN stations with a special SYNC message i e global network time If the FEN bit in MCR is set FIFO enabled MB8 is used for timer synchronization instead of MB0 This bi...

Page 567: ...e Buffers MB When the FIFO Enable bit in the FlexCAN Module Configuration Register CANx_MCR FEN bit 2 is set the RXGMASK also applies to most of the elements of the ID filter table However there is a...

Page 568: ...the RxFIFO If CANx_MCR FEN 0 then the Rx FIFO is disabled and thus the masks RXGMASK RX14MASK and RX15MASK do not affect it Enable Rx Individual Mask Registers If the Backwards Compatibility Configura...

Page 569: ...ure Setting the BCC bit in MCR causes the RX15MASK register to have no effect on the module operation When the BCC bit is negated RX15MASK is used as acceptance mask for the Identifier in Message Buff...

Page 570: ...Status Register is updated to reflect Error Active state If the value of TX_ERR_COUNTER increases to be greater than 255 the FLT_CONF field in the Error and Status Register is updated to reflect Bus...

Page 571: ...be cleared by writing 1 to them writing 0 has no effect See Section 25 5 11 Interrupts for more details Offset 0x001C Access Read write 0 1 2 3 4 5 6 7 8 9 10 11 12 13 14 15 R 0 0 0 0 0 0 0 0 0 0 0 0...

Page 572: ...effect 0 No such occurrence 1 The Tx error counter transition from 96 to 96 RWRN_INT RWRN_INT Rx Warning Interrupt Flag If the WRN_EN bit in MCR is asserted the RWRN_INT bit is set when the RX_WRN fl...

Page 573: ...on 0 No such occurrence 1 TX_Err_Counter 96 RX_WRN Rx Error Counter This bit indicates when repetitive errors are occurring during message reception 0 No such occurrence 1 Rx_Err_Counter 96 IDLE CAN b...

Page 574: ...tate Value Meaning 00 Error Active 01 Error Passive 1X Bus Off Offset 0x0024 Access Read write 0 1 2 3 4 5 6 7 8 9 10 11 12 13 14 15 R BUF 63M BUF 62M BUF 61M BUF 60M BUF 59M BUF 58M BUF 57M BUF 56M B...

Page 575: ...the MCR is set Abort enabled while the IFLAG2 bit is set for a MB configured as Tx the writing access done by CPU into the corresponding MB will be blocked Offset 0x0028 Access Read write 0 1 2 3 4 5...

Page 576: ...ficant interrupt flags BUF7I BUF0I is changed to support the FIFO operation BUF7I BUF6I and BUF5I indicate operating conditions of the FIFO while BUF4I to BUF0I are not used Offset 0x002C Access Read...

Page 577: ...nterrupt 0 No such occurrence 1 The corresponding MB has successfully completed transmission or reception BUF7I Buffer MB7 Interrupt or FIFO Overflow If the FIFO is not enabled this bit flags the inte...

Page 578: ...e of checking incoming frames against a table of IDs as many as 8 extended IDs or 16 standard IDs or 32 8 bit ID slices each one with its own individual mask register Simultaneous reception through FI...

Page 579: ...ring the Tx buffers With this extended ID concept the arbitration process is based on the full 32 bit word However the actual transmitted ID continues to have 11 bits for standard frames and 29 bits f...

Page 580: ...st number buffer is transmitted first When LBUF and LPRIO_EN are both negated the MB with the lowest ID is transmitted first but If LBUF is negated and LPRIO_EN is asserted the PRIO bits augment the I...

Page 581: ...set in the Interrupt Flag register and an interrupt is generated if allowed by the corresponding Interrupt Mask register bit Upon receiving the MB interrupt the CPU should service the received frame...

Page 582: ...ull the matching algorithm will always look for a matching MB outside the FIFO region When the frame is received it is temporarily stored in a hidden auxiliary MB called Serial Message Buffer SMB The...

Page 583: ...mask bit is negated the corresponding ID bit is don t care Please note that the Individual Mask registers are implemented in RAM so they are not initialized out of reset Also they can only be program...

Page 584: ...et the frame was transmitted If the corresponding IFLAG is reset the CPU must wait for it to be set and then the CPU must read the CODE field to check if the MB was aborted CODE 1001 or it was transmi...

Page 585: ...e for example that the FIFO is disabled and the second and the fifth MBs of the array are programmed with the same ID and FlexCAN has already received and stored messages into these two MBs Suppose no...

Page 586: ...is also generated when five frames are accumulated in the FIFO A powerful filtering scheme is provided to accept only frames intended for the target application thus reducing the interrupt servicing w...

Page 587: ...CPU Note that for filtering formats A and B it is possible to select whether remote frames are accepted or not For format C remote frames are always accepted if they match the ID 25 5 9 2 Overload fr...

Page 588: ...me handled by the CAN engine Eqn 25 1 A bit time is subdivided into three segments1 reference Figure 25 17 and Table 25 21 SYNC_SEG This segment has a fixed length of one time quantum Signal edges are...

Page 589: ...ble 25 21 Time Segment Syntax Syntax Description SYNC_SEG System expects transitions to occur on the bus during this period Transmit Point A node in transmit mode transfers a new value to the CAN bus...

Page 590: ...er CAN bit must be 8 so the oscillator clock frequency should be at least 8 times the CAN bit rate The minimum frequency ratio specified in Table 25 23 can be achieved by choosing a high enough periph...

Page 591: ...er mode is entered when the MCR MDIS bit is asserted If the module is disabled during Freeze Mode it requests to disable the clocks to the CAN Protocol Interface CPI and Message Buffer Management MBM...

Page 592: ...t In this case the CPU must read the IFLAG registers to determine which MB caused the interrupt The other 5 interrupt sources Bus Off Error Tx Warning Rx Warning and Wake Up generate interrupts like t...

Page 593: ...lying soft reset The clock source CLK_SRC bit should be selected while the module is in Disable Mode After the clock source is selected and the module is enabled MDIS bit negated FlexCAN automatically...

Page 594: ...h the last event FlexCAN attempts to synchronize to the CAN bus 25 6 2 FlexCAN addressing and RAM size configurations There are three RAM configurations that can be implemented within the FlexCAN modu...

Page 595: ...s signifies the module to which the signal applies Thus CS0_x specifies that the CS0 signal applies to DSPI module 0 1 etc A block diagram of the DSPI is shown in Figure 26 1 Figure 26 1 DSPI block di...

Page 596: ...tes on a per frame basis Six clock and transfer attribute registers Serial clock with programmable polarity and phase Programmable delays CS to SCK delay SCK to CS delay Delay between frames Programma...

Page 597: ...enter in parallel to the DSPI being in one of its module specific modes 26 3 1 Master mode Master mode allows the DSPI to initiate and control serial communication In this mode the SCK CSn and SOUT si...

Page 598: ...l is a slave select input signal that allows an SPI master to select the DSPI as the target for transmission CS0_x must be configured as input and pulled high If the internal pullup is being used then...

Page 599: ...e CS5_x signal is used to select the slave device that receives the current transfer CS5_x is a strobe signal used by external logic for deglitching of the CS signals When the DSPI is in master mode a...

Page 600: ...Transfer Attributes Register 1 DSPIx_CTAR1 on page 602 0x14 DSPI Clock and Transfer Attributes Register 2 DSPIx_CTAR2 on page 602 0x18 DSPI Clock and Transfer Attributes Register 3 DSPIx_CTAR3 on page...

Page 601: ...0 0 0 0 0 0 0 0 0 0 1 Figure 26 3 DSPI Module Configuration Register DSPIx_MCR Table 26 3 DSPIx_MCR field descriptions Field Description MSTR Master slave mode select Configures the DSPI for master m...

Page 602: ...rom the transfer that generated the overflow is ignored or put in the shift register If the ROOE bit is set the incoming data is put in the shift register If the ROOE bit is cleared the incoming data...

Page 603: ...X FIFO Counter The CLR_TXF bit is always read as zero 0 Do not clear the TX FIFO Counter 1 Clear the TX FIFO Counter CLR_RXF Clear RX FIFO CLR_RXF is used to flush the RX FIFO Writing a 1 to CLR_RXF c...

Page 604: ...ers are used to set the slave transfer attributes See the individual bit descriptions for details on which bits are used in slave modes When the DSPI is configured as an SPI master the CTAS field in t...

Page 605: ...odified Timing Format Enable bits should be set 0 The baud rate is computed normally with a 50 50 duty cycle 1 The baud rate is doubled with the duty cycle depending on the Baud Rate Prescaler FMSZ Fr...

Page 606: ...the prescaler value for the delay between the last edge of SCK and the negation of PCS This field is only used in Master Mode The table below lists the prescaler values See the ASC 0 3 field descript...

Page 607: ...r SCK Delay Scaler The ASC field selects the scaler value for the After SCK Delay This field is only used in Master Mode The After SCK Delay is the delay between the last edge of SCK and the negation...

Page 608: ...s computed according to the following equation Eqn 26 4 See Section 26 6 4 2 CS to SCK delay tCSC for more details Table 26 6 DSPI SCK duty cycle DBR CPHA PBR SCK duty cycle 0 any any 50 50 1 0 00 50...

Page 609: ...0 128 1110 32768 0111 256 1111 65536 Table 26 9 DSPI After SCK delay scaler ASC After SCK delay scaler value ASC After SCK delay scaler value 0000 2 1000 512 0001 4 1001 1024 0010 8 1010 2048 0011 16...

Page 610: ...011 2048 0100 16 1100 4096 0101 32 1101 8192 0110 64 1110 16384 0111 128 1111 32768 Table 26 12 DSPI SCK duty cycle DBR CPHA PBR SCK duty cycle 0 any any 50 50 1 0 00 50 50 1 0 01 33 66 1 0 10 40 60 1...

Page 611: ...0 128 1110 32768 0111 256 1111 65536 Table 26 15 DSPI After SCK delay scaler ASC After SCK delay scaler value ASC After SCK delay scaler value 0000 2 1000 512 0001 4 1001 1024 0010 8 1010 2048 0011 16...

Page 612: ...ect This register may not be writable in Module Disable mode due to the use of power saving mechanisms Table 26 17 DSPI baud rate scaler BR Baud rate scaler value BR Baud rate scaler value 0000 2 1000...

Page 613: ...ils When the EOQF bit is set the TXRXS bit is automatically cleared 0 EOQ is not set in the executing command 1 EOQ bit is set in the executing SPI command Note EOQF does not function in slave mode TF...

Page 614: ...O counter Indicates the number of valid entries in the TX FIFO The TXCTR is incremented every time the DSPI _PUSHR is written The TXCTR is decremented every time an SPI command is executed and the SPI...

Page 615: ...Enables the EOQF flag in the DSPIx_SR to generate an interrupt request 0 EOQF interrupt requests are disabled 1 EOQF interrupt requests are enabled TFUF_RE Transmit FIFO underflow request enable The...

Page 616: ...g in the DSPIx_SR to generate a request The RFDF_DIRS bit selects between generating an interrupt request or a DMA request 0 RFDF interrupt requests or DMA requests are disabled 1 RFDF interrupt reque...

Page 617: ...ing table shows how the CTAS values map to the DSPIx_CTARs There are eight DSPIx_CTARs in the device DSPI implementation Note Use in SPI master mode only EOQ End of queue Provides a means for host sof...

Page 618: ...TLB entry for DSPIx_POPR as guarded PCSx Peripheral chip select x Selects which CSx signals are asserted for the transfer 0 Negate the CSx signal 1 Assert the CSx signal Note Use in SPI master mode o...

Page 619: ...ng purposes Each register is an entry in the RX FIFO The DSPIx_RXFR registers are read only Reading the DSPIx_RXFRn registers does not alter the state of the RX FIFO The device uses four registers to...

Page 620: ...and the 16 bit shift register in the slave are linked by the SOUT_x and SIN_x signals to form a distributed 32 bit register When a data transfer operation is performed data is serially shifted a pred...

Page 621: ...sable modes are module specific modes whereas debug mode is device specific The module specific modes are determined by bits in the DSPIx_MCR Debug mode is a mode that the entire device can enter in p...

Page 622: ...ing If the MCU enters debug mode while the FRZ bit in the DSPIx_MCR is set the DSPI stops all serial transfers and enters a stopped state If the MCU enters debug mode while the FRZ bit is cleared the...

Page 623: ...master mode and slave mode The FIFO operations are similar for the master mode and slave mode The main difference is that in master mode the DSPI initiates and controls the transfer according to the...

Page 624: ...f the DSPIx_TXFRs and TXNXTPTR are undefined When the RX FIFO is disabled the RFDF RFOF and RXCTR fields in the DSPIx_SR behave as if there is a one entry FIFO but the contents of the DSPIx_RXFRs and...

Page 625: ...r The TX FIFO is flushed by writing a 1 to the CLR_TXF bit in DSPIx_MCR If an external SPI bus master initiates a transfer with a DSPI slave while the slave s DSPI TX FIFO is empty the transmit FIFO u...

Page 626: ...data returned from reading an empty RX FIFO is undetermined See Section 26 5 8 DSPI POP RX FIFO Register DSPIx_POPR for more information on DSPIx_POPR When the RX FIFO is not empty the RX FIFO drain f...

Page 627: ...tionship between these variables is given in the following formula Table 26 27 shows an example of the computed after SCK delay 26 6 4 4 Delay after transfer tDT The delay after transfer is the length...

Page 628: ...Peripheral chip select strobe timing The delay between the assertion of the CSx signals and the assertion of CS5_x is selected by the PCSSCK field in the DSPIx_CTAR based on the following formula At...

Page 629: ...er must be identical for the master device and the slave device to ensure proper transmission The DSPI supports four different transfer formats Classic SPI with CPHA 0 Classic SPI with CPHA 1 Modified...

Page 630: ...n their serial data output signals For the rest of the frame the master and the slave sample their SIN_x pins on the odd numbered clock edges and changes the data on their SOUT_x pins on the even numb...

Page 631: ...CK_x the master and slave sample their SIN_x pins For the rest of the frame the master and the slave change the data on their SOUT_x pins on the odd numbered clock edges and sample their SIN_x pins on...

Page 632: ...The slave samples the master SOUT_x signal on every odd numbered SCK_x edge The slave also places new data on the slave SOUT_x on every odd numbered clock edge The master places its second data bit on...

Page 633: ...T signal on the odd numbered SCK edges starting with the third SCK edge The slave samples the last bit on the last edge of the SCK The master samples the last slave SOUT bit one half SCK cycle after t...

Page 634: ...the SPI configuration by setting the CONT bit in the SPI command When the CONT bit 0 the DSPI drives the asserted chip select signals to their idle states in between frames The idle states of the chip...

Page 635: ...ore CTAR is switched When the CONT bit 1 and the CS signals for the next transfer are different from the present transfer the CS signals behave as if the CONT bit was not set NOTE You must fill the TX...

Page 636: ...TX FIFO must be cleared before initiating any SPI configuration transfer When the DSPI is in SPI configuration CTAR0 is used initially At the start of each SPI frame transfer the CTAR specified by th...

Page 637: ...uous SCK format with continuous selection enabled Figure 26 24 Continuous SCK timing diagram CONT 1 26 6 7 Interrupt DMA requests The DSPI has five conditions that can generate interrupt requests only...

Page 638: ...d the TFFF_RE bit in the DSPIx_RSER is set The TFFF_DIRS bit in the DSPIx_RSER selects whether a DMA request or an interrupt request is generated 26 6 7 3 Transfer Complete Interrupt Request TCF The t...

Page 639: ...e FIFOs in the DSPI has exceeded its capacity The FIFO overrun request is generated by logically ORing together the RX FIFO overflow and TX FIFO underflow signals 26 6 8 Power saving features The DSPI...

Page 640: ...4 The eDMA continues to fill TX FIFO until it is full or step 5 occurs 5 Disable DSPI DMA transfers by disabling the DMA enable request for the DMA channel assigned to TX FIFO and RX FIFO This is done...

Page 641: ...6 5 33 MHz 3 56 MHz 2 13 MHz 1 52 MHz 8 4 MHz 2 67 MHz 1 60 MHz 1 15 MHz 16 2 MHz 1 33 MHz 800 kHz 571 kHz 32 1 MHz 670 kHz 400 kHz 285 kHz 64 500 kHz 333 kHz 200 kHz 142 kHz 128 250 kHz 166 kHz 100 k...

Page 642: ...for each FIFO The pointer to the first in entry in each FIFO is memory mapped For the TX FIFO the first in pointer is the transmit next pointer TXNXTPTR For the RX FIFO the first in pointer is the po...

Page 643: ...FIFO base 4 TXNXTPTR The memory address of the last in entry in the TX FIFO is computed by the following equation Last in entry address TXFIFO base 4 TXCTR TXNXTPTR 1 modulo TXFIFO depth where TXFIFO...

Page 644: ...Serial Peripheral Interface DSPI MPC5606BK Microcontroller Reference Manual Rev 2 642 Freescale Semiconductor RXCTR receive FIFO counter POPNXTPTR pop next pointer RX FIFO depth receive FIFO depth imp...

Page 645: ...MPC5606BK Microcontroller Reference Manual Rev 2 Freescale Semiconductor 643 Timers...

Page 646: ...MPC5606BK Microcontroller Reference Manual Rev 2 644 Freescale Semiconductor This page is intentionally left blank...

Page 647: ...eMIOS Periodic Interrupt Timer PIT The microcontroller also has a Real Time Clock Autonomous Periodic Interrupt RTC API module The main purpose of this is to provide a periodic device wakeup source 27...

Page 648: ...Chapter 27 Timers MPC5606BK Microcontroller Reference Manual Rev 2 646 Freescale Semiconductor Figure 27 1 Interaction between timers and relevant peripherals...

Page 649: ...e used as a common timing reference These counter buses can be used in combination with the individual channel counters to provide advanced features such as centre aligned PWM with dead time insertion...

Page 650: ...8 PE 2 UC 3 PA 3 PB 11 PC 8 UC 19 PE 3 UC 4 PA 4 PB 12 UC 20 PE 4 UC 5 PA 5 PB 13 UC 21 PE 5 UC 6 PA 6 PB 14 UC 22 PE 6 PF 5 PE 8 UC 7 PA 7 PB 15 PC 9 UC 23 PE 7 PF 6 PE 9 UC 8 PA 8 UC 24 PE 11 PG 10...

Page 651: ...esired The PIT is also used to trigger other events Four of the PIT channels can be used as an eDMA trigger Two PIT channels can be used to trigger a CTU ADC conversion single Two PIT channels one per...

Page 652: ...erface signals 27 3 3 Memory map and register definition The STM programming model has fourteen 32 bit registers The STM registers can only be accessed using 32 bit word accesses Attempted references...

Page 653: ...page 653 0x0038 STM Channel 2 Compare Register STM_CMP2 on page 654 0x003C Reserved 0x0040 STM Channel 3 Control Register STM_CCR3 on page 652 0x0044 STM Channel 3 Interrupt Register STM_CIR3 on page...

Page 654: ...2 0xFF Divide system clock by 256 FRZ Freeze Allows the timer counter to be stopped when the device enters debug mode 0 STM counter continues to run in debug mode 1 STM counter is stopped in debug mod...

Page 655: ...0 0 0 0 0 0 0 0 0 0 0 0 Figure 27 4 STM Channel Control Register STM_CCRn Table 27 6 STM_CCRn field descriptions Field Description CEN Channel Enable 0 The channel is disabled 1 The channel is enable...

Page 656: ...n debug mode otherwise it continues to run in debug mode The counter rolls over at 0xFFFF_FFFF to 0x0000_0000 with no restrictions at this boundary The STM has four identical compare channels Each cha...

Page 657: ...an be connected to the CTU Both eMIOS blocks can be synchronized One global prescaler 16 bit data registers 10 16 bit wide counter buses Counter buses B C D and E can be driven by Unified Channel 0 8...

Page 658: ...idth Modulation Buffered These modes are described in Section 27 4 4 1 1 UC modes of operation Each channel can have a specific set of modes implemented according to device requirements If an unimplem...

Page 659: ...mpare Ch0 Ch1 Ch2 Ch3 Ch4 Ch5 Ch6 Ch7 Ch8 Ch9 Ch10 Ch11 Ch12 Ch13 Ch14 Ch15 Ch16 Ch17 Ch18 Ch19 Ch24 Ch20 Ch21 Ch22 Ch23 Global Prescaler 8 bit Counter Counter Bus_B Counter Bus_A Counter Bus_C Counte...

Page 660: ...map and register description 27 4 3 1 Memory maps The overall address map organization is shown in Table 27 9 27 4 3 1 1 Unified Channel memory map Table 27 9 eMIOS memory map Base addresses 0xC3FA_0...

Page 661: ...MIOS UC B Register EMIOSB n on page 663 0x08 eMIOS UC Counter Register EMIOSCNT n on page 664 0x0C eMIOS UC Control Register EMIOSC n on page 665 0x10 eMIOS UC Status Register EMIOSS n on page 669 0x1...

Page 662: ...nel FREN bit is cleared 1 Stops Unified Channels operation when in Debug mode and the FREN bit is set in the EMIOSC n register 0 Exit freeze state GTBE Global Time Base Enable The GTBE bit is used to...

Page 663: ...F7 F6 F5 F4 F3 F2 F1 F0 W Reset 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 Figure 27 9 eMIOS Global FLAG EMIOSGFLAG Register Table 27 13 EMIOSGFLAG field descriptions Field Description Fn Channel n Flag bit Add...

Page 664: ...less stated otherwise transfer occurs immediately Address eMIOS base address 0x0C 0 1 2 3 4 5 6 7 8 9 10 11 12 13 14 15 R CHDIS31 CHDIS30 CHDIS29 CHDIS28 CHDIS27 CHDIS26 CHDIS25 CHDIS24 CHDIS23 CHDIS2...

Page 665: ...ng and reading accesses for all operation modes For more information see Section 27 4 4 1 1 UC modes of operation Depending on the channel configuration it may have EMIOSB register or not This means t...

Page 666: ...is implemented then the counter is present otherwise it is absent Table 27 16 EMIOSA n EMIOSB n and EMIOSALTA n values assignment Operation mode Register access write read write read alt write alt re...

Page 667: ...ontrol Register EMIOSC n Table 27 17 EMIOSC n field descriptions Field Description FREN Freeze Enable bit The FREN bit if set and validated by FRZ bit in EMIOSMCR register allows the channel to enter...

Page 668: ...t signal or a DMA request signal or a CTU trigger signal The type of signal to be generated is defined by the DMA bit 1 Enable FLAG will generate an interrupt request or DMA request or a CTU trigger 0...

Page 669: ...the EDPOL bit asserts which edge triggers either the internal counter or an input capture or a FLAG When not shown in the mode of operation description this bit has no effect 1 Trigger on a rising edg...

Page 670: ...ut Compare 0000100 Input Pulse Width Measurement 0000101 Input Period Measurement 0000110 Double Action Output Compare with FLAG set on B match 0000111 Double Action Output Compare with FLAG set on bo...

Page 671: ...d descriptions Field Description OVR Overrun bit The OVR bit indicates that FLAG generation occurred when the FLAG bit was already set 1 Overrun has occurred 0 Overrun has not occurred OVFL Overflow b...

Page 672: ...ified channel can generate its own time base3 The eMIOS block is reset at positive edge of the clock synchronous reset All registers are cleared on reset 27 4 4 1 Unified Channel UC Each Unified Chann...

Page 673: ...mode In GPIO mode all input capture and output compare functions of the UC are disabled the internal counter EMIOSCNT n register is cleared and disabled All control bits remain accessible In order to...

Page 674: ...DSEL bit selects whether the output flip flop is toggled or the value in EDPOL is transferred to it Along with the match the FLAG bit is set to indicate that the output compare match has occurred Writ...

Page 675: ...th no need of further writes to EMIOSA n register The FLAG is set at the same time a match occurs see Figure 27 22 NOTE The channel internal counter in SAOC mode is free running It starts counting as...

Page 676: ...d into register A2 and at the same time the FLAG bit is set and the content of register B2 is transferred to register B1 and to register A1 If subsequent input capture events occur while the correspon...

Page 677: ...oherent data is required for any reason the sequence of reads should be inverted therefore EMIOSB n should be read prior to EMIOSA n register Note that even in this case B1 register updates will be bl...

Page 678: ...alues in register A2 and B1 respectively In order to allow coherent data reading EMIOSA n forces A1 content be transferred to B1 register and disables transfers between B2 and B1 These transfers are d...

Page 679: ...urs and is disabled on the next B match Comparators A and B are enabled and disabled independently The output flip flop is set to the value of EDPOL when a match occurs on comparator A and to the comp...

Page 680: ...le action output compare with FLAG set on both matches selected counter bus 0x000500 0x001000 0x001100 0x001000 0x001100 A1 value1 B1 value2 0xxxxxxx 0x001100 0x001100 0x001100 0xxxxxxx 0x001000 0x001...

Page 681: ...DE 6 is set In this case the internal counter clears as soon as the match signal occurs The channel FLAG is set at the same time the match occurs Note that by having the internal counter cleared as so...

Page 682: ...A1 sets the FLAG and changes the counter direction from increment to decrement A match between register B1 and the internal counter changes the counter direction from decrement to increment and sets t...

Page 683: ...C n channel register When entering in MCB mode if up counter is selected by MODE 4 0 MODE 0 6 101000b the internal counter starts counting from its current value to up direction until A1 match occurs...

Page 684: ...h start if MODE 5 is 0 If MODE 5 is set to 1 flags are also generated at the cycle boundary Figure 27 33 Modulus Counter Buffered MCB Up Down mode Figure 27 34 describes in more detail the A1 register...

Page 685: ...r can be used to disable the update of A1 register Figure 27 35 MCB Mode A1 Register Update in Up Down Counter mode 27 4 4 1 1 9 Output Pulse Width and Frequency Modulation Buffered OPWFMB mode This m...

Page 686: ...e leads to unpredictable results If you want to configure the module for OPWFMB mode ensure that the B1 register is modified before the mode is set Figure 27 36 describes the operation of the OPWFMB m...

Page 687: ...its OU n of EMIOSOUDIS register can be used to control the update of these registers thus allowing to delay the A1 and B1 registers update for synchronization purposes In Figure 27 38 it is assumed th...

Page 688: ...an be generated for any A1 value greater or equal to B1 Figure 27 39 OPWFMB mode from 100 to 0 duty cycle A 0 duty cycle signal is generated if A1 0x0 as shown in Figure 27 39 cycle 9 In this case B1...

Page 689: ...l counter For a leading edge dead time insertion the output PWM duty cycle is equal to the difference between register A1 and register B1 and for a trailing edge dead time insertion the output PWM dut...

Page 690: ...A1 match sets the internal counter to 0x1 When a match occurs between register B1 and the internal time base the output flip flop is set to the value of the EDPOL bit In the following match between r...

Page 691: ...the selected time base the internal counter is set to 0x1 and B1 matches are enabled When the match between register B1 and the selected time base occurs the output flip flop is set to the complement...

Page 692: ...MA force a transition in the output flip flop to the opposite of EDPOL In trail dead time insertion the output flip flop is forced to the value of EDPOL bit If bit FORCMB is set the output flip flop v...

Page 693: ...of 100 duty cycle the transition from EDPOL to the opposite of EDPOL may be obtained by forcing pin using FORCMA or FORCMB or both NOTE If A1 is set to 0x1 at OPWMCB entry the 100 duty cycle may not...

Page 694: ...defined by the EDPOL bit If EDPOL is zero a negative edge occurs when A1 matches the selected counter bus and a positive edge occurs when B1 matches the selected counter bus The A1 and B1 registers a...

Page 695: ...0 Figure 27 44 OPWMB mode matches and flags Note that the output pin transitions are based on the negedges of the A1 and B1 match signals Figure 27 44 shows in cycle n 1 the value of A1 register being...

Page 696: ...B1 match Note also that if B1 is set to 0x9 for instance B1 match does not occur thus a 0 duty cycle signal is generated 1 4 match A1 negedge detection 8 A1 value 0x000004 A1 match A1 match negedge d...

Page 697: ...t registers loaded with 0x0 will not produce matches if the timebase is driven by a channel in MCB mode A1 is not buffered as the shift of a PWM channel must not be modified while the PWM signal is be...

Page 698: ...ote that the load of B2 content on B1 register at an A match is not inhibited due to a simultaneous FORCMA FORCMB assertion If both FORCMA and FORCMB are asserted simultaneously the output pin goes to...

Page 699: ...value1 write to B2 0x000400 B1 value B2 value2 0x000700 Match B1 write to A1 0xxxxxxx 0x000400 0x001000 0x000700 and B2 0x001000 Match A1 Match B1 Match A1 Notes 1 EMIOSA n A1 2 EMIOSB n B2 for write...

Page 700: ...ounter overflows occurs the new pin value is validated In this case it is transmitted as a pulse edge to the edge detector If the opposite edge appears on the pin before validation overflow the counte...

Page 701: ...e desired value for prescaling rate at UCPRE 0 1 bits in EMIOSC n register 3 Enable channel prescaler by writing 1 at UCPREN bit in EMIOSC n register 4 Enable global prescaler by writing 1 at GPREN bi...

Page 702: ...any update in the prescaling rate is desired 1 Write 0 at GPREN bit in EMIOSMCR thus disabling global prescaler 2 Write the desired value for prescaling rate at GPRE 0 7 bits in EMIOSMCR 3 Enable glob...

Page 703: ...uring the clock prescaler ratio Figure 27 52 shows an example of a time base with prescaler ratio equal to one NOTE MCB and OPWFMB modes have a different behavior Figure 27 52 Time base period when ru...

Page 704: ...e note 1 Note 1 When a match occurs the first system clock cycle is used to clear the internal counter and at the next edge of prescaler clock enable 1 2 the counter will start counting 1 2 3 0 FLAG s...

Page 705: ...a disabled B2 to B1 transfer 27 4 5 2 3 Channel Modes initialization The following basic steps summarize basic output mode startup assuming the channels are initially in GPIO mode 1 global Disable Glo...

Page 706: ...me applications such as in OPWFM B mode or whenever the output channel is intended to run the timebase itself The flags can be configured at any time 27 5 Periodic Interrupt Timer PIT 27 5 1 Introduct...

Page 707: ...dress 0xC3FF_0000 Address offset Use Location 0x000 PIT Module Control Register PITMCR on page 706 0x004 0x0FC Reserved 0x100 0x10C Timer Channel 0 See Table 27 24 0x110 0x11C Timer Channel 1 See Tabl...

Page 708: ...riod for the timer interrupts Offset 0x000 Access Read Write 0 1 2 3 4 5 6 7 8 9 10 11 12 13 14 15 R 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 W Reset 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 16 17 18 19 20 21 22 23 24...

Page 709: ...upt and loads this register value again Writing a new value to this register does not restart the timer instead the value is loaded once the timer expires To abort the current cycle and start a timer...

Page 710: ...mer Control Register TCTRL Table 27 28 TCTRL field descriptions Field Description TIE Timer Interrupt Enable Bit 0 Interrupt requests from Timer x are disabled 1 Interrupt will be requested whenever T...

Page 711: ...previous one is cleared If desired the current counter value of the timer can be read via the CVAL registers The counter period can be restarted by first disabling then enabling the timer with the TEN...

Page 712: ...rrupt flags TIF are set to 1 when a timeout occurs on the associated timer and are cleared to 0 by writing a 1 to that TIF bit 27 5 6 Initialization and application information 27 5 6 1 Example config...

Page 713: ...s started by writing a 1 to bit TEN in the TCTRL1 register Timer 3 shall be used only for triggering Therefore Timer 3 is started by writing a 1 to bit TEN in the TCTRL3 register bit TIE stays at 0 Th...

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Page 715: ...MPC5606BK Microcontroller Reference Manual Rev 2 Freescale Semiconductor 713 ADC system...

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Page 717: ...g multiplexer selection Four internal channels optionally used to support externally multiplexed inputs providing transparent control for additional ADC channels Each of the four channels supports as...

Page 718: ...log switch eMIOS PIT INTC D A MUX 32 MUX 16 ADC_0 10 bit Ch0 trig Ch22 trig Ch24 trig Ch31 trig PIT3 16 precision channels same pins as ADC 10b ADC_1_P 15 Ch 15 ADC_1_P 0 Ch 0 2 interrupts ADC_EOC ADC...

Page 719: ...ded for external channel selection and are available as alternate functions on GPIO The MA 0 2 are controlled by the ADC itself and are set automatically by the hardware A conversion timing register f...

Page 720: ...performed only once At the end of each conversion the digital result of the conversion is stored in the corresponding data register Example 28 1 One Shot Mode MODE 0 Channels A B C D E F G H are pres...

Page 721: ...annel in the injected chain is converted normal conversion resumes from the channel at which the normal conversion was aborted as shown in Figure 28 3 Figure 28 3 Injected sample conversion sequence T...

Page 722: ...nterrupt of the current aborted conversion is not generated but an ECH interrupt is generated to signal the end of the chain When a chain conversion abort is requested ABORTCHAIN bit is set while an i...

Page 723: ...f INPSAMP is less than or equal to 06h otherwise it is 1 INPSAMP must be greater than or equal to 3 hardware requirement The total evaluation phase duration is INPCMP must be greater than or equal to...

Page 724: ...CH Tconv s Tconv Tck 6 0 167 4 0 5 0 583 3 500 1 1 667 0 2 333 14 000 7 0 143 4 0 5 0 500 3 500 1 1 429 0 2 000 14 000 8 0 125 5 0 5 0 563 4 500 1 1 250 0 1 875 15 000 16 0 063 9 1 0 500 8 000 1 0 625...

Page 725: ...ng and conversion timing at 5 V for ADC_1 Clock MHz Tck s INPSAMPLE1 1 Where INPSAMPLE 8 Ndelay2 2 Where INPSAMP 6 N 0 5 INPSAMP 6 N 1 Tsample 3 3 Where Tsample INPSAMP N Tck Must be 500 ns Tsample Tc...

Page 726: ...063 11 1 0 625 10 000 0 3 000 1 3 688 59 000 20 0 050 13 1 0 600 12 000 0 2 400 1 3 050 61 000 1 Where INPSAMPLE 8 2 Where INPSAMP 6 N 0 5 INPSAMP 6 N 1 3 Where Tsample INPSAMP N Tck Must be 600 ns Ta...

Page 727: ...conversion is triggered then the injected channel conversion chain is aborted and only the CTU triggered conversion proceeds By aborting the injected conversion the MSR JSTART is reset That abort is s...

Page 728: ...fields one per channel type in the PSCR make it possible to select different presampling values for each type 28 3 6 Programmable analog watchdog 28 3 6 1 Introduction The analog watchdogs are used f...

Page 729: ...ide the threshold values The channel monitoring is enabled by setting the bit corresponding to channel 15 in the CWENR If a converted value for a particular channel lies outside the range specified by...

Page 730: ...0 2 Two registers named CEOCFR 0 2 Channel Pending Registers and IMR Interrupt Mask Register are provided in order to check and enable the interrupt request to INT module Interrupts can be individual...

Page 731: ...e ongoing conversion Otherwise the ongoing operation should be aborted manually by resetting the NSTART bit and using the ABORTCHAIN bit MSR ADCSTATUS bit is set only when ADC enters power down mode A...

Page 732: ...CEOCFR2 on page 741 0x0020 Interrupt Mask Register IMR on page 743 0x0024 Channel Interrupt Mask Register CIMR0 on page 744 0x0028 Channel Interrupt Mask Register CIMR1 on page 744 0x002C Channel Int...

Page 733: ...ected Conversion Mask Register 2 JCMR2 on page 760 0x00C0 0x00C3 Reserved 0x00C4 Decode Signals Delay Register DSDR on page 761 0x00C8 Power down Exit Delay Register PDEDR on page 762 0x00CC 0x00FF Re...

Page 734: ...1 on page 763 0x01A8 Channel 42 Data Register CDR42 on page 763 0x01AC Channel 43 Data Register CDR43 on page 763 0x01B0 Channel 44 Data Register CDR44 on page 763 0x01B4 Channel 45 Data Register CDR4...

Page 735: ...5 on page 763 0x0230 Channel 76 Data Register CDR76 on page 763 0x0234 Channel 77 Data Register CDR77 on page 763 0x0238 Channel 78 Data Register CDR78 on page 763 0x023C Channel 79 Data Register CDR7...

Page 736: ...page 765 0x02C8 Channel Watchdog Selection Register 6 CWSELR6 on page 765 0x02CC Channel Watchdog Selection Register 7 CWSELR7 on page 765 0x02D0 Channel Watchdog Selection Register 8 CWSELR8 on page...

Page 737: ...chdog Threshold Interrupt Status Register WTISR on page 746 0x0034 Watchdog Threshold Interrupt Mask Register WTIMR on page 747 0x0038 0x003F Reserved 0x0040 DMA Enable Register DMAE on page 748 0x004...

Page 738: ...3 0x0120 Channel 8 Data Register CDR8 on page 763 0x0124 Channel 9 Data Register CDR9 on page 763 0x0128 Channel 10 Data Register CDR10 on page 763 0x012C Channel 11 Data Register CDR11 on page 763 0x...

Page 739: ...dog Enable Register 0 CWENR0 on page 773 0x02E4 Channel Watchdog Enable Register 1 CWENR1 on page 773 0x02F0 Analog Watchdog Out of Range register 0 AWORR0 on page 775 0x02F4 Analog Watchdog Out of Ra...

Page 740: ...GEN Injection external trigger enable 0 External trigger disabled for channel injection 1 External trigger enabled for channel injection JEDGE Injection trigger edge selection Edge selection for exter...

Page 741: ...0 0 0 CTUSTART W Reset 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 16 17 18 19 20 21 22 23 24 25 26 27 28 29 30 31 R CHADDR 0 0 0 ACK0 0 0 ADCSTATUS W Reset 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 1 Figure 28 10 Main Statu...

Page 742: ...Wait state The ADC is waiting for an external multiplexer This only occurs when the DSDR register is non zero 011 Reserved 100 Sample The ADC is sampling the analog signal 101 Reserved 110 Conversion...

Page 743: ...15 precision channels ADC_0 CEOCFR1 End of conversion pending interrupt for channel 32 to 59 standard channels ADC_0 CEOCFR2 End of conversion pending interrupt for channel 64 to 95 external multiplex...

Page 744: ...H44 EOC_CH43 EOC_CH42 EOC_CH41 EOC_CH40 EOC_CH39 EOC_CH38 EOC_CH37 EOC_CH36 EOC_CH35 EOC_CH34 EOC_CH33 EOC_CH32 W w1c w1c w1c w1c w1c w1c w1c w1c w1c w1c w1c w1c w1c w1c w1c w1c Reset 0 0 0 0 0 0 0 0...

Page 745: ...16 17 18 19 20 21 22 23 24 25 26 27 28 29 30 31 R EOC_CH79 EOC_CH78 EOC_CH77 EOC_CH76 EOC_CH75 EOC_CH74 EOC_CH73 EOC_CH72 EOC_CH71 EOC_CH70 EOC_CH69 EOC_CH68 EOC_CH67 EOC_CH66 EOC_CH65 EOC_CH64 W w1c...

Page 746: ...led MSKECH Mask for end of chain conversion ECH interrupt When set the ECH interrupt is enabled ADC Register Description ADC_0 CIMR0 Enable bit for channel 0 to 15 precision channels ADC_0 CIMR1 Enabl...

Page 747: ...d write 0 1 2 3 4 5 6 7 8 9 10 11 12 13 14 15 R 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 W Reset 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 16 17 18 19 20 21 22 23 24 25 26 27 28 29 30 31 R 0 0 0 0 0 0 0 0 CIM 39 CIM 38...

Page 748: ...set 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 16 17 18 19 20 21 22 23 24 25 26 27 28 29 30 31 R 0 0 0 0 WDG 5H WDG 5L WDG 4H WDG 4L WDG 3H WDG 3L WDG 2H WDG 2L WDG 1H WDG 1L WDG 0H WDG 0L W w1c w1c w1c w1c w1c...

Page 749: ...er WTISR Table 28 20 ADC_1 WTISR field descriptions Field Description WDGxH This corresponds to the interrupt generated on the converted value being higher than the programmed higher threshold for x 0...

Page 750: ...set the interrupt is enabled Address Base 0x0034 Access User read write 0 1 2 3 4 5 6 7 8 9 10 11 12 13 14 15 R 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 W Reset 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 16 17 18 19 20 2...

Page 751: ...Figure 28 25 DMA Enable Register DMAE Table 28 23 DMAE field descriptions Field Description DCLR DMA clear sequence enable 0 DMA request cleared by Acknowledge from DMA controller 1 DMA request clear...

Page 752: ...12 13 14 15 R 0 0 0 0 DMA 59 DMA 58 DMA 57 DMA 56 DMA 55 DMA 54 DMA 53 DMA 52 DMA 51 DMA 50 DMA 49 DMA 48 W Reset 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 16 17 18 19 20 21 22 23 24 25 26 27 28 29 30 31 R DMA...

Page 753: ...6 DMA 85 DMA 84 DMA 83 DMA 82 DMA 81 DMA 80 W Reset 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 16 17 18 19 20 21 22 23 24 25 26 27 28 29 30 31 R DMA 79 DMA 78 DMA 77 DMA 76 DMA 75 DMA 74 DMA 73 DMA 72 DMA 71 DMA...

Page 754: ...0 0 0 1 1 1 1 1 1 1 1 1 1 16 17 18 19 20 21 22 23 24 25 26 27 28 29 30 31 R 0 0 0 0 0 0 THRL W Reset 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 Figure 28 30 ADC_0 Threshold Register THRHLR 0 5 Table 28 26 ADC_0...

Page 755: ...PREVAL0 PRE CONV W Reset 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 Figure 28 32 Presampling Control Register PSCR Table 28 28 PSCR field descriptions Field Description PREVAL2 Internal voltage selection for pre...

Page 756: ...11 12 13 14 15 R 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 W Reset 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 16 17 18 19 20 21 22 23 24 25 26 27 28 29 30 31 R PRES 15 PRES 14 PRES 13 PRES 12 PRES 11 PRES 10 PRES 9 PRES 8...

Page 757: ...Register 1 PSR1 for ADC_1 Address Base 0x008C Access User read write 0 1 2 3 4 5 6 7 8 9 10 11 12 13 14 15 R PRES 95 PRES 94 PRES 93 PRES 92 PRES 91 PRES 90 PRES 89 PRES 88 PRES 87 PRES 86 PRES 85 PR...

Page 758: ...0 11 12 13 14 15 R 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 W Reset 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 16 17 18 19 20 21 22 23 24 25 26 27 28 29 30 31 R INPLATCH 0 OFFSHIFT1 1 Available only on CTR0 0 INPCMP 0 IN...

Page 759: ...ion channels ADC_0 NCMR1 Enable bits of normal sampling for channel 32 to 59 standard channels ADC_0 NCMR2 Enable bits of normal sampling for channel 64 to 95 external multiplexed channels ADC_1 NCMR0...

Page 760: ...ess User read write 0 1 2 3 4 5 6 7 8 9 10 11 12 13 14 15 R 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 W Reset 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 16 17 18 19 20 21 22 23 24 25 26 27 28 29 30 31 R 0 0 0 0 0 0 0 0 CH...

Page 761: ...759 NOTE The implicit channel conversion priority in the case in which all channels are selected is the following ADCn_P 0 x ADCn_S 0 y ADCn_X 0 z The channels always start with 0 the lowest index Ta...

Page 762: ...injected sampling for channel 32 to 39 standard channels Address Base 0x00B4 Access User read write 0 1 2 3 4 5 6 7 8 9 10 11 12 13 14 15 R 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 W Reset 0 0 0 0 0 0 0 0 0 0...

Page 763: ...38 CH37 CH36 CH35 CH34 CH33 CH32 W Reset 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 Figure 28 44 Injected Conversion Mask Register 1 JCMR1 for ADC_1 Address Base 0x00BC Access User read write 0 1 2 3 4 5 6 7 8 9...

Page 764: ...decode signals and the start of the sampling phase It is used to take into account the settling time of the external multiplexer The decode signal delay is calculated as DSD 1 frequency of ADC clock N...

Page 765: ...er down bit reset and the start of conversion The delay is to allow time for the ADC power supply to settle before commencing conversions The power down delay is calculated as PDED 1 frequency of ADC...

Page 766: ...16 17 18 19 20 21 22 23 24 25 26 27 28 29 30 31 R CDATA 0 9 MCR WLSIDE 1 0 0 0 0 0 0 W Reset 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 Figure 28 48 Channel Data Register CDR 0 95 Address See Table 28 10 Access...

Page 767: ...s 0 Converted data has not been overwritten 1 Previous converted data has been overwritten before having been read RESULT This bit reflects the mode of conversion for the corresponding channel 00 Data...

Page 768: ...42 CWSELR field descriptions ADC_0 Field Description WSEL_CHn Channel Watchdog select for channel n 000 THRHLR0 register is selected 001 THRHLR1 register is selected 010 THRHLR2 register is selected 0...

Page 769: ...9 30 31 R 0 WSEL_CH35 0 WSEL_CH34 0 WSEL_CH33 0 WSEL_CH32 W Reset 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 Figure 28 52 Channel Watchdog Select Register 4 CWSELR4 ADC_0 Table 28 44 CWSELR4 field descriptions A...

Page 770: ...27 28 29 30 31 R 0 WSEL_CH51 0 WSEL_CH50 0 WSEL_CH49 0 WSEL_CH48 W Reset 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 Figure 28 54 Channel Watchdog Select Register 6 CWSELR6 ADC_0 Table 28 46 CWSELR6 field descri...

Page 771: ...9 30 31 R 0 WSEL_CH67 0 WSEL_CH66 0 WSEL_CH65 0 WSEL_CH64 W Reset 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 Figure 28 56 Channel Watchdog Select Register 8 CWSELR8 ADC_0 Table 28 48 CWSELR8 field descriptions A...

Page 772: ...30 31 R 0 WSEL_CH83 0 WSEL_CH82 0 WSEL_CH81 0 WSEL_CH80 W Reset 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 Figure 28 58 Channel Watchdog Select Register 10 CWSELR10 ADC_0 Table 28 50 CWSELR10 field descriptions...

Page 773: ...0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 Figure 28 60 Channel Watchdog Select Register 0 CWSELR0 ADC_1 Table 28 52 CWSELR0 field descriptions ADC_1 Field Description WSEL_CHn Channel Watchdog select for channel...

Page 774: ...R 0 0 WSEL_CH35 0 0 WSEL_CH34 0 0 WSEL_CH33 0 0 WSEL_CH32 W Reset 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 Figure 28 62 Channel Watchdog Select Register 4 CWSELR4 ADC_1 Table 28 54 CWSELR4 field descriptions A...

Page 775: ...ENR2 Watchdog enable bits for channel 64 to 95 external multiplexed channels ADC_1 CWENR0 Watchdog enable bits for channel 0 to 15 precision channels ADC_1 CWENR1 Watchdog enable bits for channel 32 t...

Page 776: ...1 2 3 4 5 6 7 8 9 10 11 12 13 14 15 R 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 W Reset 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 16 17 18 19 20 21 22 23 24 25 26 27 28 29 30 31 R 0 0 0 0 0 0 0 0 CWEN 39 CWEN 38 CWEN 37...

Page 777: ...R_CH5 AWOR_CH4 AWOR_CH3 AWOR_CH2 AWOR_CH1 AWOR_CH0 W Reset 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 Figure 28 68 Analog Watchdog Out of Range Register 0 AWORR0 Address Base 0x02F4 Access User read write 0 1 2...

Page 778: ...1 2 3 4 5 6 7 8 9 10 11 12 13 14 15 R AWOR_CH95 AWOR_CH94 AWOR_CH93 AWOR_CH92 AWOR_CH91 AWOR_CH90 AWOR_CH89 AWOR_CH88 AWOR_CH87 AWOR_CH86 AWOR_CH85 AWOR_CH84 AWOR_CH83 AWOR_CH82 AWOR_CH81 AWOR_CH80 W...

Page 779: ...utput is a combination of 64 generic value input flags events connected to different timers in the system One event configuration register dedicated to each timer event to define the corresponding ADC...

Page 780: ...9 10 11 12 13 14 15 R 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 W Reset 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 16 17 18 19 20 21 22 23 24 25 26 27 28 29 30 31 R TM CLR_FLAG 1 1 This bit implementation is generic base...

Page 781: ...ersions until the device is reset 29 5 Functional description This peripheral is used to synchronize ADC conversions with timer events from eMIOS or PIT When a timer event occurs the CTU triggers an A...

Page 782: ..._25 26 eMIOS 0 Channel_26 27 eMIOS 0 Channel_27 28 eMIOS 0 Channel_28 29 eMIOS 0 Channel_29 30 eMIOS 0 Channel_30 31 eMIOS 0 Channel_31 32 eMIOS 1 Channel_0 33 eMIOS 1 Channel_1 34 eMIOS 1 Channel_2 3...

Page 783: ...of the CTU_EVTCFGR register These bits are implemented for only those input flags to which PIT flags are connected Providing these bits offers the option of clearing PIT flags by software 29 5 1 Chan...

Page 784: ...CH6 6 ADC1_P 6 CH6 6 ADC0_P 7 CH7 7 ADC1_P 7 CH7 7 ADC0_P 8 CH8 8 ADC1_P 8 CH8 8 ADC0_P 9 CH9 9 ADC1_P 9 CH9 9 ADC0_P 10 CH10 10 ADC1_P 10 CH10 10 ADC0_P 11 CH11 11 ADC1_P 11 CH11 11 ADC0_P 12 CH12 1...

Page 785: ...or this channel ADC0_S 14 CH46 46 ADC0_S 15 CH47 47 ADC0_S 16 CH48 48 ADC0_S 17 CH49 49 ADC0_S 18 CH50 50 ADC0_S 19 CH51 51 ADC0_S 20 CH52 52 ADC0_S 21 CH53 53 ADC0_S 22 CH54 54 ADC0_S 23 CH55 55 ADC0...

Page 786: ...Chapter 29 Cross Triggering Unit CTU MPC5606BK Microcontroller Reference Manual Rev 2 786 Freescale Semiconductor This page is intentionally left blank...

Page 787: ...MPC5606BK Microcontroller Reference Manual Rev 2 Freescale Semiconductor 787 Memory...

Page 788: ...MPC5606BK Microcontroller Reference Manual Rev 2 788 Freescale Semiconductor This page is intentionally left blank...

Page 789: ...ture The primary function of the flash memory module is to serve as electrically programmable and erasable nonvolatile memory Nonvolatile memory may be used for instruction and or data storage The mod...

Page 790: ...memory core The memory interface is also the interface between the flash memory module and a platform flash memory controller It contains the ECC logic and redundancy logic A platform flash memory con...

Page 791: ...read page buffering may be done in the platform flash memory controller Each read of the flash memory module retrieves a page or four consecutive words 128 bits of information The address for each wo...

Page 792: ...ion 30 4 2 1 CFlash module sectorization The CFlash module supports 1 MB of user memory plus 16 KB of test memory a portion of which is One Time Programmable by the user An extra 16 KB sector is avail...

Page 793: ...protection A software mechanism is provided to independently lock unlock each block in low and mid address space against program and erase 30 4 3 TestFlash block A TestFlash block is available in bot...

Page 794: ...FF 8192 bytes Reserved 0x402000 0x403CFF 7424 bytes User OTP area 0x403D00 0x403DE7 232 bytes CFLASH_NVLML CFlash Nonvolatile Low Mid Address Space Block Locking Register 0x403DE8 0x403DEF 8 bytes CFL...

Page 795: ...rase The shadow sector contains specified data that are needed for user features The user area of shadow sector may be used for user defined functions possibly to store boot code other configuration w...

Page 796: ...nvalid locations occur when blocks that do not exist in non 2n array sizes are addressed Attempted interlock writes to invalid locations will result in an interlock occurring but attempts to program t...

Page 797: ...in any case be completed and the power down mode will be entered only after the programming ends The user should realize that if the flash memory module is put in power down mode and the interrupt ve...

Page 798: ...8 0x0014 CFlash High Address Space Block Select Register CFLASH_HBS on page 819 0x0018 CFlash Address Register CFLASH_ADR on page 820 0x0028 0x0038 Reserved 0x003C CFlash User Test 0 register CFLASH_U...

Page 799: ...30 5 1 CFlash register description 30 5 1 1 CFlash Module Configuration Register CFLASH_MCR The CFlash Module Configuration Register is used to enable and monitor all modify operations of the flash me...

Page 800: ...tes that all previous reads from the last reset or clearing of EDC were not corrected through ECC 0 Reads are occurring normally 1 An ECC single error occurred and was corrected during a previous read...

Page 801: ...dress space is active for program and erase The value in PEAS is captured and held with the first interlock write done for Modify operations The value of PEAS is retained between sampling events that...

Page 802: ...tegrity check or margin read PEG is set to 1 when the operation is completed regardless the occurrence of any error The presence of errors can be detected only comparing checksum value stored in UMIRS...

Page 803: ...V may be set under one of the following conditions Erase ERS 1 ESUS 0 UT0 AIE 0 Program ERS 0 ESUS 0 PGM 1 UT0 AIE 0 In normal operation a 1 to 0 transition of EHV with DONE high and ESUS low terminat...

Page 804: ...ough a priority mechanism among the bits The bit changing priorities are detailed in Table 30 13 If the user attempts to write two or more CFLASH_MCR bits simultaneously then only the bit with the low...

Page 805: ...L The CFlash Low Mid Address Space Block Locking register provides a means to protect blocks from being modified These bits along with bits in the CFLASH_SLL register determine if the block is locked...

Page 806: ...ock of Test and Shadow address space from program and erase erase is any case forbidden for Test block A value of 1 in the TSLK register signifies that the Test shadow sector is locked for program and...

Page 807: ...ys be 1 independent of the TestFlash block and register writes will have no effect MLK is not writable unless LME is high 0 Mid address space block is unlocked and can be modified also if CFLASH_SLL S...

Page 808: ...to the CFLASH_LML register 0 Low Address Locks are disabled TSLK MLK1 0 and LLK15 0 cannot be written 1 Low Address Locks are enabled TSLK MLK1 0 and LLK15 0 can be written TSLK Test Shadow Address S...

Page 809: ...gh 0 Mid address space block is unlocked and can be modified also if CFLASH_SLL SMLK 0 1 Mid address space block is locked and cannot be modified LLK Low Address Space Block Lock These bits are used t...

Page 810: ...gh address space from program and erase HLK11 8 are not used for this memory cut A value of 1 in a bit of the HLK register signifies that the corresponding block is locked for program and erase A valu...

Page 811: ...lash module the CFLASH_NVHBL register content is read and loaded into the CFLASH_HBL The CFLASH_NVHBL register is a 64 bit register of which the 32 most significant bits 63 32 are don t care and event...

Page 812: ...re used to lock the blocks of high address space from program and erase HLK11 8 are not used for this memory cut A value of 1 in a bit of the HLK register signifies that the corresponding block is loc...

Page 813: ...tion occurs For SLE the password 0xC3C33333 must be written to the CFLASH_SLL register 0 Secondary Low Mid Address Locks are disabled STSLK SMK1 0 and SLK15 0 cannot be written 1 Secondary Low Mid Add...

Page 814: ...ASH_LML MLK 0 1 Mid address space block is locked and cannot be modified SLK Secondary Low Address Space Block Lock These bits are used as an alternate means to lock the blocks of low address space fr...

Page 815: ...e flash memory module the CFLASH_NVSLL register content is read and loaded into the CFLASH_SLL The CFLASH_NVSLL register is a 64 bit register of which the 32 most significant bits 63 32 are don t care...

Page 816: ...an alternate means to lock the block of Test and Shadow address space from program and erase erase is any case forbidden for Test block A value of 1 in the STSLK register signifies that the Test shad...

Page 817: ...SH_LML MLK 0 1 Mid address space block is locked and cannot be modified SLK Secondary Low Address Space Block Lock These bits are used as an alternate means to lock the blocks of low address space fro...

Page 818: ...ted or if a high voltage operation is suspended In the event that blocks are not present due to configuration or total memory size the corresponding MSL bits will default to not selected and will not...

Page 819: ...f 1 in the select register signifies that the block is selected for erase A value of 0 in the select register signifies that the block is not selected for erase The reset value for the select register...

Page 820: ...LASH_MCR RWE 1 or the address of a failure that may have occurred in a FPEC operation CFLASH_MCR PEG 0 The Address Register also provides the first address at which an ECC single error correction occu...

Page 821: ...field descriptions Field Description UTE User Test Enable This status bit gives indication when User Test is enabled All bits in CFLASH_UT0 2 and CFLASH_UMISR0 4 are locked when this bit is 0 The meth...

Page 822: ...checks or margin read The default sequence AIS 0 is meant to replicate sequences normal user code follows and thoroughly checks the read propagation paths This sequence is proprietary The alternative...

Page 823: ...word The User Test 2 Register is not accessible whenever CFLASH_MCR DONE or CFLASH_UT0 AID are low reading returns indeterminate data while writing has no effect Offset 0x00040 Access Read write 0 1...

Page 824: ...eading returns indeterminate data while writing has no effect Offset 0x00044 Access Read write 0 1 2 3 4 5 6 7 8 9 10 11 12 13 14 15 R DAI 63 48 W Reset 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 16 17 18 19 20...

Page 825: ...s indeterminate data while writing has no effect Offset 0x00048 Access Read write 0 1 2 3 4 5 6 7 8 9 10 11 12 13 14 15 R MS0 31 16 W Reset 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 16 17 18 19 20 21 22 23 24 2...

Page 826: ...urns indeterminate data while writing has no effect Offset 0x0004C Access Read write 0 1 2 3 4 5 6 7 8 9 10 11 12 13 14 15 R MS0 63 48 W Reset 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 16 17 18 19 20 21 22 23 2...

Page 827: ...urns indeterminate data while writing has no effect Offset 0x00050 Access Read write 0 1 2 3 4 5 6 7 8 9 10 11 12 13 14 15 R MS0 95 80 W Reset 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 16 17 18 19 20 21 22 23 2...

Page 828: ...ble word The CFLASH_UMISR4 is not accessible whenever CFLASH_MCR DONE or CFLASH_UT0 AID are low reading returns indeterminate data while writing has no effect Offset 0x00054 Access Read write 0 1 2 3...

Page 829: ...MS 143 128 W Reset 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 Figure 30 20 CFlash User Multiple Input Signature Register 4 CFLASH_UMISR4 Table 30 31 CFLASH_UMISR4 field descriptions Field Description MS 159 128...

Page 830: ...0 1 1 1 0 1 1 0 1 16 17 18 19 20 21 22 23 24 25 26 27 28 29 30 31 R PWD 15 0 W Reset 1 1 1 1 1 0 1 0 1 1 0 0 1 1 1 0 Figure 30 21 CFlash Nonvolatile Private Censorship Password 0 Register NVPWD0 Tabl...

Page 831: ...es the 32 LSB of the Censorship Control Word of the device The NVSCC0 is a nonvolatile register located in the Shadow sector it is read during the reset phase of the flash memory module and the protec...

Page 832: ...ese bits represent the 16 LSB of the Censorship Control Word CCW If CW15 0 0x55AA and NVSCC1 NVSCC0 the Censored Mode is disabled If CW15 0 0x55AA or NVSCC1 NVSCC0 the Censored Mode is enabled Offset...

Page 833: ...18 19 20 21 22 23 24 25 26 27 28 29 30 31 R 1 1 1 1 1 1 1 1 1 1 1 1 1 1 1 1 W Reset 1 1 1 1 1 1 1 1 1 1 1 1 1 1 1 1 Figure 30 25 CFlash Nonvolatile User Options register NVUSRO Table 30 36 NVUSRO fiel...

Page 834: ...previous reads If an ECC single error detection and correction occurred the EDC bit is set to 1 This bit must then be cleared or a reset must occur before this bit will return to a 0 state This bit ma...

Page 835: ...rase Access Space PEAS indicates which space is valid for program and erase operations main array space or shadow test space PEAS 0 indicates that the main address space is active for all flash memory...

Page 836: ...eck or margin read PEG is set to 1 when the operation is completed regardless the occurrence of any error The presence of errors can be detected only comparing checksum value stored in UMIRS0 1 Aborti...

Page 837: ...r one of the following conditions Erase ERS 1 ESUS 0 DFLASH_UT0 AIE 0 Program ERS 0 ESUS 0 PGM 1 DFLASH_UT0 AIE 0 In normal operation a 1 to 0 transition of EHV with DONE high and ESUS low terminates...

Page 838: ...through a priority mechanism among the bits The bit changing priorities are detailed in the Table 30 41 If the user attempts to write two or more DFLASH_MCR bits simultaneously then only the bit with...

Page 839: ...h Low Mid Address Space Block Locking register provides a means to protect blocks from being modified These bits along with bits in the DFLASH_SLL register determine if the block is locked from progra...

Page 840: ...its TestFlash block value The default value of the TSLK bit assuming erased fuses would be locked TSLK is not writable unless LME is high 0 Test Shadow address space block is unlocked and can be modif...

Page 841: ...lash memory module the DFLASH_NVLML register content is read and loaded into the DFLASH_LML The DFLASH_NVLML register is a 64 bit register of which the 32 most significant bits 63 32 are don t care an...

Page 842: ...stFlash block value The default value of the TSLK bit assuming erased fuses would be locked TSLK is not writable unless LME is high 0 Test Shadow address space block is unlocked and can be modified al...

Page 843: ...k status Offset 0x000C Access Read write 0 1 2 3 4 5 6 7 8 9 10 11 12 13 14 15 R SLE 0 0 0 0 0 0 0 0 0 0 STSLK 0 0 0 0 W Reset Defined by DFLASH_NVSLL at DFlash Test Sector Address 0xC03DF8 This locat...

Page 844: ...t to go back to its TestFlash block value The default value of the STSLK bit assuming erased fuses would be locked STSLK is not writable unless SLE is high 0 Test Shadow address space block is unlocke...

Page 845: ...he flash memory module the DFLASH_NVSLL register content is read and loaded into the DFLASH_SLL The DFLASH_NVSLL register is a 64 bit register of which the 32 most significant bits 63 32 are don t car...

Page 846: ...it to go back to its TestFlash block value The default value of the STSLK bit assuming erased fuses would be locked STSLK is not writable unless SLE is high 0 Test Shadow address space block is unlock...

Page 847: ...ield descriptions Field Description LSL Low Address Space Block Select A value of 1 in the select register signifies that the block is selected for erase A value of 0 in the select register signifies...

Page 848: ...FLASH_MCR PEG cleared The Address Register also provides the first address at which an ECC single error correction occurs DFLASH_MCR EDC set if the device is configured to show this feature The ECC do...

Page 849: ...nabled All bits in DFLASH_UT0 2 and DFLASH_UMISR0 4 are locked when this bit is 0 This bit is not writable to a 1 but may be cleared The reset value is 0 The method to set this bit is to provide a pas...

Page 850: ...o be used during array integrity checks or margin read The default sequence AIS 0 is meant to replicate sequences normal user code follows and thoroughly checks the read propagation paths This sequenc...

Page 851: ...The User Test 2 Register is not accessible whenever DFLASH_MCR DONE or DFLASH_UT0 AID are low reading returns indeterminate data while writing has no effect Address offset 0x00040 Access Read write 0...

Page 852: ...ate data while writing has no effect Offset 0x00044 Reset value 0x0000_0000 0 1 2 3 4 5 6 7 8 9 10 11 12 13 14 15 R DAI 63 48 W Reset 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 16 17 18 19 20 21 22 23 24 25 26 2...

Page 853: ...terminate data while writing has no effect Address offset 0x00048 Reset value 0x0000_0000 0 1 2 3 4 5 6 7 8 9 10 11 12 13 14 15 R MS 31 16 W Reset 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 16 17 18 19 20 21 22...

Page 854: ...ndeterminate data while writing has no effect Address offset 0x0004C Reset value 0x0000_0000 0 1 2 3 4 5 6 7 8 9 10 11 12 13 14 15 R MS 63 48 W Reset 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 16 17 18 19 20 21...

Page 855: ...ndeterminate data while writing has no effect Address offset 0x00050 Reset value 0x0000_0000 0 1 2 3 4 5 6 7 8 9 10 11 12 13 14 15 R MS 95 80 W Reset 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 16 17 18 19 20 21...

Page 856: ...on for odd and even double word The DFLASH_UMISR4 Register is not accessible whenever DFLASH_MCR DONE or DFLASH_UT0 AID are low reading returns indeterminate data while writing has no effect Address o...

Page 857: ...module is not fetchable when a modify operation is active and these commands must be executed from another memory internal SRAM or another flash memory module Address offset 0x00058 Reset value 0x0000...

Page 858: ...e modified until the MCR DONE bit or UT0 AID is high In general each modify operation is completed through a sequence of four steps 1 Wait for operation completion wait for the MCR DONE bit or UT0 AID...

Page 859: ...ess bits 22 3 at this time c The flash memory module latches data written as well d This write is referred to as a program data interlock write An interlock write may be as large as 64 bits and as sma...

Page 860: ...n Start do Loop to wait for DONE 1 tmp MCR Read MCR while tmp 0x00000400 status MCR 0x00000200 Check PEG flag MCR 0x00000010 Reset EHV in MCR Operation End MCR 0x00000000 Reset PGM in MCR Deselect Ope...

Page 861: ...may not abort an erase sequence while in erase suspend Example 30 2 Erase of sectors B0F1 and B0F2 MCR 0x00000004 Set ERS in MCR Select Operation LMS 0x00000006 Set LSL2 1 in LMS Select Sectors to er...

Page 862: ...dule integrity by putting the flash memory module in User Test mode Three kinds of test can be performed Array integrity self check Margin read ECC logic check The User Test Mode is equivalent to a Mo...

Page 863: ...ssing only 4 Write a logic 1 to the UT0 AIE bit to start the Array Integrity Check 5 Wait until the UT0 AID bit goes high 6 Compare UMISR0 4 content with the expected result 7 Write a logic 0 to the U...

Page 864: ...y writing 1s to the appropriate bit s in the LMS register Note that Lock and Select are independent If a block is selected and locked no Array Integrity Check will occur 3 Set T0 AIS bit for a sequent...

Page 865: ...e the ECC logic of the whole page 2 double words The results of the ECC logic check can be verified by reading the MISR value The ECC logic check operation consists of the following sequence of events...

Page 866: ...algorithms The flash memory module supports one ECC algorithm All 1s No Error A modified Hamming code is used that ensures the all erased state that is 0xFFFF FFFF data is a valid state and will not c...

Page 867: ...volatile modify protection registers is the protected state All the nonvolatile modify protection registers can be programmed through a normal double word program operation at the related locations i...

Page 868: ...ed by erasing the Shadow Sector The nonvolatile Censored Mode Registers are physically located in the Shadow Sector their bits can be programmed to 0 and restored to 1 by erasing the Shadow Sector The...

Page 869: ...AM memory controller PRAM AHB to IPS APB bus controller PBRIDGE for access to on and off platform slave modules Interrupt Controller INTC 4 channel System Timers STM Software Watchdog Timer SWT Error...

Page 870: ...nd the other bank is connected to the optional data flash memory The memory controller capabilities vary between the two banks with each bank s functionality optimized with the typical use cases assoc...

Page 871: ...rt for reporting of single and multi bit flash memory ECC events Typical operating configuration loaded into programming model by system reset 30 7 2 Memory map and register description Two memory map...

Page 872: ...oller module is defined by the platform flash controller registers of code array0 The 32 bit memory map for the platform flash memory controller control registers is shown in Table 30 60 The base addr...

Page 873: ...orts p0 and the optional p1 For the platform flash memory controller module the fields associated with AHB port p1 are ignored The register is described in Figure 30 42 and Table 30 61 NOTE Do not exe...

Page 874: ...or reads This field must be set to a value corresponding to the operating frequency of the PFlash and the actual read access time of the PFlash The required settings are documented in the device datas...

Page 875: ...fetching is triggered by a data read access 1 If page buffers are enabled B0_P0_BFE 1 prefetching is triggered by any data read access B0_P0_IPFE Bank0 Port 0 Instruction Prefetch Enable This field en...

Page 876: ...C 0 0 0 0 0 0 0 BK1_RWWC 0 0 0 0 0 0 B1_P0_BFE W Reset 1 0 0 0 0 0 0 0 1 0 0 0 0 0 0 1 Figure 30 43 PFlash Configuration Register 1 PFCR1 Table 30 62 PFCR1 field descriptions Field Description BK1_APC...

Page 877: ...wait states are added This field is ignored in single bank flash memory configurations Note The setting for RWSC must be the same as APC BK1_RWWC Bank1 Read While Write Control This 3 bit field define...

Page 878: ...ss 0x203E00 Figure 30 44 PFlash Access Protection Register PFAPR Table 30 63 PFAPR field descriptions Field Description M2PFD eDMA Master 2 Prefetch Disable This field controls whether prefetching may...

Page 879: ...ead accesses may be performed by this master 10 Only write accesses may be performed by this master 11 Both read and write accesses may be performed by this master M0AP e200z0 core Master 0 Access Pro...

Page 880: ...egister 0 PFCR0 and Section 30 7 2 2 2 Platform Flash Configuration Register 1 PFCR1 Access protections may be applied on a per master basis for both reads and writes to support security and privilege...

Page 881: ...te response 30 8 4 Write cycles Write cycles are initiated by the platform flash memory controller The platform flash memory controller then waits for the appropriate number of write wait states befor...

Page 882: ...to the requesting bus master As noted in Section 30 8 7 Flash error response operation a page buffer is not marked as valid if the flash memory array access terminated with any type of transfer error...

Page 883: ...ormance by lowering average read latency In order for prefetching to occur a number of control bits must be enabled Specifically the global buffer enable PFCRn Bx_Py_BFE must be set the prefetch limit...

Page 884: ...d data Since this bank does not support prefetching the read data for the referenced address is bypassed directly back to the AHB data bus The page is also loaded into the temporary data register and...

Page 885: ...ate a pseudo address phase cycle to retry the read reference and sends the registered information to the array Once the retried address phase is complete the read is processed normally and once the da...

Page 886: ...l primary wait states These wait states are applied to the initial access of a burst fetch or to single beat read accesses on the AHB system bus Note that the wait state specification consists of two...

Page 887: ...K Microcontroller Reference Manual Rev 2 Freescale Semiconductor 887 Table 30 67 Extended additional wait state encoding Memory address haddr 25 24 Additional wait states added to those specified by h...

Page 888: ...Chapter 30 Flash Memory MPC5606BK Microcontroller Reference Manual Rev 2 888 Freescale Semiconductor This page is intentionally left blank...

Page 889: ...n in Table 31 3 The internal SRAM has no registers Registers for the SRAM ECC are located in the ECSM see Chapter 34 Error Correction Status Module ECSM for more information Table 31 1 SRAM behavior i...

Page 890: ...he following occurs 1 The ECC mechanism checks the entire 32 bit data bus for errors detecting and either correcting or flagging errors 2 The write data bytes 1 or 2 byte segment are merged with the c...

Page 891: ...f a R W operation Because the ECC bits can contain random data after the device is powered on the SRAM must be initialized by executing 32 bit write operations prior to any read accesses This is also...

Page 892: ...M MPC5606BK Microcontroller Reference Manual Rev 2 892 Freescale Semiconductor entire 32 bits 8 or 16 bits a read modify write operation is generated that checks the ECC value upon the read See Sectio...

Page 893: ...MPC5606BK Microcontroller Reference Manual Rev 2 Freescale Semiconductor 893 Integrity...

Page 894: ...MPC5606BK Microcontroller Reference Manual Rev 2 894 Freescale Semiconductor This page is intentionally left blank...

Page 895: ...n in Figure 32 1 Figure 32 1 Register Protection block diagram Please see the Registers Under Protection appendix for the list of protected registers 32 2 Features The Register Protection includes the...

Page 896: ...rs and is transparent for all read write operations Area 2 spans 2 KB starting at address 0x1800 It is a reserved area that cannot be accessed Area 3 spans 6 KB starting at address 0x2000 and is a mir...

Page 897: ...not all accessed bytes are locked Accessing unimplemented 32 bit registers in Areas 4 and 5 results in a transfer error 32 5 1 Memory map Table 32 1 gives an overview on the Register Protection regist...

Page 898: ...ister SLBR0 1535 These registers hold the soft lock bits for the protected registers in memory area 1 Figure 32 3 gives some examples how SLBRn SLB and MRn go together Address 0x3800 0x3DFF Access Rea...

Page 899: ...bit Protected address SLBR0 SLB0 MR0 SLBR0 SLB1 MR1 SLBR0 SLB2 MR2 SLBR0 SLB3 MR3 SLBR1 SLB0 MR4 SLBR1 SLB1 MR5 SLBR1 SLB2 MR6 SLBR1 SLB3 MR7 SLBR2 SLB0 MR8 Address 0x3FFC Access Read Always Superviso...

Page 900: ...b0 no matter what software is writing to 32 6 2 Change lock settings To change the setting whether an address is locked or unlocked the corresponding SLBRn SLBm bit needs to be changed This can be don...

Page 901: ...6 Change lock settings for 16 bit protected addresses On the right side of Figure 32 6 it is shown that the data written to SLBRn SLB 0 is automatically written to SLBRn SLB 1 also This is done as the...

Page 902: ...ed protection The data written to SLBRn SLB 0 is mirrored to SLBRn SLB 1 as the corresponding register is 16 bit protected The data written to SLBRn SLB 2 is blocked as the corresponding register is u...

Page 903: ...ays 0b0 shown in bold When doing a 32 bit write access to address 0x200C only lock bits SLBR3 SLB 3 2 are set while bits SLBR3 SLB 1 0 stay 0b0 NOTE Lock bits can only be set via writes to the mirror...

Page 904: ...is word is ignored 6 If writing to a soft lock register in area 4 with the hard lock bit being set a transfer error is asserted 7 Any write operation in any access mode to area 3 while GCR HLB is set...

Page 905: ...bits 0 15 SIUL PCR12 16 C3F90000 058 bits 0 15 SIUL PCR13 16 C3F90000 05A bits 0 15 SIUL PCR14 16 C3F90000 05C bits 0 15 SIUL PCR15 16 C3F90000 05E bits 0 15 SIUL PCR16 16 C3F90000 060 bits 0 15 SIUL...

Page 906: ...0 0D2 bits 0 15 SIUL PCR74 16 C3F90000 0D4 bits 0 15 SIUL PCR75 16 C3F90000 0D6 bits 0 15 SIUL PCR76 16 C3F90000 0D8 bits 0 15 SIUL PCR77 16 C3F90000 0DA bits 0 15 SIUL PCR78 16 C3F90000 0DC bits 0 15...

Page 907: ...122 bits 0 15 SIUL PCR114 16 C3F90000 124 bits 0 15 SIUL PCR115 16 C3F90000 126 bits 0 15 SIUL PCR123 16 C3F90000 136 bits 0 15 SIUL PCR124 16 C3F90000 138 bits 0 15 SIUL PCR125 16 C3F90000 13A bits...

Page 908: ...F90000 1000 bits 0 31 SIUL IFMC1 32 C3F90000 1004 bits 0 31 SIUL IFMC2 32 C3F90000 1008 bits 0 31 SIUL IFMC3 32 C3F90000 100C bits 0 31 SIUL IFMC4 32 C3F90000 1010 bits 0 31 SIUL IFMC5 32 C3F90000 101...

Page 909: ..._MC 32 C3FDC000 038 bits 0 31 MC ME ME_RUN3_MC 32 C3FDC000 03C bits 0 31 MC ME ME_HALT_MC 32 C3FDC000 040 bits 0 31 MC ME ME_STOP_MC 32 C3FDC000 048 bits 0 31 MC ME ME_STANDBY_MC 32 C3FDC000 054 bits...

Page 910: ...C ME ME_PCTL 88 91 32 C3FDC000 118 bits 0 31 MC ME ME_PCTL 92 95 32 C3FDC000 11C bits 0 31 MC ME ME_PCTL 104 107 32 C3FDC000 128 bits 0 31 Clock Generation Module 3 registers to protect MC CGM CGM_OC_...

Page 911: ...eference Manual Rev 2 Freescale Semiconductor 911 MC PCU PCONF2 32 C3FE8000 008 bits 0 31 MC PCU PCONF3 32 C3FE8000 00C bits 0 31 Table 32 5 Protected registers continued Module Register Protected siz...

Page 912: ...Chapter 32 Register Protection MPC5606BK Microcontroller Reference Manual Rev 2 912 Freescale Semiconductor This page is intentionally left blank...

Page 913: ...counter clock is the undivided slow internal RC oscillator 128 kHz SIRC no other clock source can be selected Programmable selection of window mode or regular servicing Programmable selection of rese...

Page 914: ...n in Table 33 1 The reset values of SWT_CR SWT_TO and SWT_WN are device specific These values are determined by SWT inputs Table 33 1 SWT memory map Base address 0xFFF3_8000 Address offset Register Ac...

Page 915: ...22 23 24 25 26 27 28 29 30 31 R 0 0 0 0 0 0 KEY RIA WND ITR HLK SLK CSL STP FRZ WEN W Reset 0 0 0 0 0 0 0 1 0 0 0 1 1 0 1 _ Table 33 2 SWT_CR field descriptions Field Description MAPn Master Access Pr...

Page 916: ...e status of the bit has no effect on counter clock selection on MPC5606BK device 0 System clock Not applicable in MPC5606BK 1 Oscillator clock STP Stop Mode Control Allows the watchdog timer to be sto...

Page 917: ...ure 33 4 SWT Window Register SWT_WN Table 33 3 SWT_IR field descriptions Field Description TIF Time out Interrupt Flag The flag and interrupt are cleared by writing a 1 to this bit Writing a 0 has no...

Page 918: ...en when the internal down counter is less than this value Address Base 0x0010 Access User read write 0 1 2 3 4 5 6 7 8 9 10 11 12 13 14 15 16 17 18 19 20 21 22 23 24 25 26 27 28 29 30 31 R 0 0 0 0 0 0...

Page 919: ...cally after reset is released Some devices can be configured to clear this bit automatically during the boot process The SWT_TO register holds the watchdog time out period in clock cycles unless the v...

Page 920: ...Eqn 33 1 This algorithm generates a sequence of 216 different key values before repeating The state of the key generator is held in the SWT_SK register For example if SWT_SK SK is 0x0100 then the ser...

Page 921: ...og is enabled this register is cleared The value shown in this register can lag behind the value in the internal counter for as long as 6 system plus 8 counter clock cycles The SWT_CO can be used duri...

Page 922: ...Chapter 33 Software Watchdog Timer SWT MPC5606BK Microcontroller Reference Manual Rev 2 922 Freescale Semiconductor This page is intentionally left blank...

Page 923: ...rates module enables the module address transfer attributes byte enables and write data These elements then function as inputs to the IPS peripherals IPS Inter Peripheral Subsytem AIPS interface betwe...

Page 924: ...x20 0x23 Reserved 0x24 Miscellaneous User Defined Control Register MUDCR on page 928 0x28 0x42 Reserved 0x43 ECC Configuration Register ECR on page 929 0x44 0x46 Reserved 0x47 ECC Status Register ESR...

Page 925: ...revision number The state of this register is defined by an input signal it can only be read from the IPS programming model Any attempted write is ignored 34 4 2 3 IPS On Platform Module Configuratio...

Page 926: ...1 2 3 4 5 6 7 8 9 10 11 12 13 14 15 R MC 31 16 W Reset 0 0 0 0 1 0 0 0 0 0 0 0 0 0 1 1 16 17 18 19 20 21 22 23 24 25 26 27 28 29 30 31 R MC 15 0 W Reset 1 1 1 0 0 0 0 0 0 0 0 0 0 0 0 0 Figure 34 3 IPS...

Page 927: ...34 5 MIR field descriptions Field Description FB0AI Flash Bank 0 Abort Interrupt 0 A flash bank 0 abort has not occurred 1 A flash bank 0 abort has occurred The interrupt request is negated by writin...

Page 928: ...ion Register EEGR Platform Flash ECC Address Register PFEAR Platform Flash ECC Master Number Register PFEMR Platform Flash ECC Attributes Register PFEAT Platform Flash ECC Data Register PFEDR Offset 0...

Page 929: ...gnal all non correctable memory errors In addition to the interrupt generation the ECSM captures specific information memory address attributes and data bus master number etc which may be useful for s...

Page 930: ...AT and PREDR registers 0 Reporting of non correctable SRAM errors is disabled 1 Reporting of non correctable SRAM errors is enabled EFNCR Enable Flash Non Correctable Reporting The occurrence of a non...

Page 931: ...rectable error where the combination of a properly enabled category in the ECR and the detection of the corresponding condition in the ESR produces the interrupt request The ECSM allows a maximum of o...

Page 932: ...been detected 1 A reportable single bit SRAM correction has been detected F1BC Flash Memory 1 bit Correction This bit can only be set if ECR EPF1BR is asserted The occurrence of a properly enabled si...

Page 933: ...write operation The normal ECC generation takes place in the SRAM controller but then the polarity of the bit position defined by ERRBIT is inverted to introduce a 1 bit ECC event in the SRAM After t...

Page 934: ...d parity bit are inverted to introduce a 2 bit ECC error in the SRAM After this bit has been enabled to generate a single 2 bit error it must be cleared before being set again to properly re enable th...

Page 935: ...event in the flash memory Depending on the state of the ECC Configuration Register an ECC event in the flash causes the address attributes and data associated with the access to be loaded into the PF...

Page 936: ...ast properly enabled ECC event in the flash memory Depending on the state of the ECC Configuration Register an ECC event in the flash causes the address attributes and data associated with the access...

Page 937: ...g model any attempted write is ignored SIZE AMBA AHB HSIZE 2 0 000 8 bit AMBA AHB access 001 16 bit AMBA AHB access 010 32 bit AMBA AHB access 1xx Reserved PROTECTION AMBA AHB HPROT 3 0 Protection 3 C...

Page 938: ...ring the error syndrome of the last properly enabled ECC event in the SRAM memory Depending on the state of the ECC Configuration Register an ECC event in the SRAM causes the address attributes and da...

Page 939: ...d The upper 7 bits of the syndrome specify the exact bit position in error for single bit correctable codewords and the combination of a non zero 7 bit syndrome plus overall incorrect parity bit signa...

Page 940: ...ECC Status Register to be asserted See Chapter 19 Crossbar Switch XBAR for a listing of XBAR bus master numbers This register can only be read from the IPS programming model any attempted write is ign...

Page 941: ...latform RAM ECC Master Number Register PREMR Table 34 17 PREMR field descriptions Field Description REMR SRAM ECC Master Number Register This 4 bit register contains the XBAR bus master number of the...

Page 942: ...NCE in the ECC Status Register to be asserted The data captured on a multi bit non correctable ECC error is undefined 34 4 3 Register protection Logic exists that restricts accesses to INTC ECSM MPU S...

Page 943: ...MPC5606BK Microcontroller Reference Manual Rev 2 Freescale Semiconductor 943 Debug...

Page 944: ...MPC5606BK Microcontroller Reference Manual Rev 2 944 Freescale Semiconductor This page is intentionally left blank...

Page 945: ...1 is a block diagram of the JTAG Controller JTAGC block Figure 35 1 JTAG controller block diagram 35 3 Overview The JTAGC provides the means to test chip functionality and connectivity while remainin...

Page 946: ...ontroller state machine transitions controlled by TMS Asserting power on reset results in asynchronous entry into the reset state While in reset the following actions occur The TAP controller is force...

Page 947: ...USE DR state was entered Auxiliary TAP controllers are held in RUN TEST IDLE while they are inactive 35 6 External signal description The JTAGC consists of four signals that connect to off chip develo...

Page 948: ...er is set to a logic 0 Therefore the first bit shifted out after selecting the bypass register is always a logic 0 35 7 3 Device identification register The device identification register shown in Tab...

Page 949: ...ter is loaded with the IDCODE instruction 35 8 2 IEEE 1149 1 2001 JTAG Test Access Port The JTAGC uses the IEEE 1149 1 2001 TAP for accessing registers This port can be shared with other TAP controlle...

Page 950: ...re 35 5 shows holding TMS at logic 1 while clocking TCK through a sufficient number of rising edges also causes the state machine to enter the test logic reset state Figure 35 5 IEEE 1149 1 2001 TAP c...

Page 951: ...001 defined instructions listed in Table 35 3 35 8 4 1 BYPASS instruction BYPASS selects the bypass register creating a single bit shift register path between TDI and TDO BYPASS enhances test efficien...

Page 952: ...it device identification register as the shift path between TDI and TDO This instruction allows interrogation of the MCU to determine its version number and other part identification data IDCODE is th...

Page 953: ...PCRx WPE Analog switch is disabled independent of PCRx APC Slew rate control is forced to the slowest configuration independent from PCRx SRC 1 35 8 5 Boundary scan The boundary scan technique allows...

Page 954: ...ost e200z0 OnCE debug registers are fully documented in the e200z0 Reference Manual 35 9 3 1 OnCE Command register OCMD The OnCE command register OCMD is a 10 bit shift register that receives its seri...

Page 955: ...MD Table 35 4 e200z0 OnCE register addressing RS 0 6 Register selected 000 0000 000 0001 Reserved 000 0010 JTAG ID read only 000 0011 000 1111 Reserved 001 0000 CPU Scan Register CPUSCR 001 0001 No Re...

Page 956: ...internally Any mixed operation using both the test logic and the system functional logic requires external synchronization To initialize the JTAGC module and enable access to registers the following s...

Page 957: ...SC with inputs FIRC and FXOSC to Figure 6 6 FMPLL block diagram Added Note to Section 6 8 4 1 Crystal clock monitor Note Functional FXOSC monitoring can only be guaranteed when the FXOSC frequency is...

Page 958: ...ronization of APIVAL to the RTC clock and APIVAL 1 cycles for subsequent occurrences After that interrupts are periodic in nature The minimum supported value of APIVAL is 4 Chapter 16 Enhanced Direct...

Page 959: ...eld In Section 24 10 8 LIN output compare register LINOCR in Figure 24 25 LIN output compare register LINOCR changed the footnote to If LINTCSR LTOM 0 these fields are read only Changed the first sent...

Page 960: ...m the first paragraph In Section 25 4 4 6 Rx 15 Mask RX15MASK register removed the phrase For MCUs supporting individual masks per MB from the first paragraph Removed Note in Section 25 4 4 13 Rx Indi...

Page 961: ...at request is discarded with If another CTU conversion is triggered before the end of the current CTU triggered conversion the new request is discarded In Section 28 3 5 2 Presampling channel enable s...

Page 962: ...for ADC_1 CTR1 Associated to internal standard channel 32 to 39 In Table 28 33 NCMR 0 2 register description added a row for ADC_1 NCMR1 Enable bit of normal sampling channel 32 to 39 standard channel...

Page 963: ...atform bus master assignments are device specific 0 Access for the master is not enabled 1 Access for the master is enabled In Figure 33 2 SWT Interrupt Register SWT_IR SWT Interrupt Register SWT_IR c...

Page 964: ...ifically disclaims any and all liability including without limitation consequential or incidental damages Typical parameters that may be provided in Freescale Semiconductor data sheets and or specific...

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