NXP Semiconductors MPC5605BK, Reference Manual

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Chapter 9 Reset Generation Module (MC_RGM)
MPC5606BK Microcontroller Reference Manual, Rev. 2
190 Freescale Semiconductor
Figure 9-11. Reset configuration timing
9.4.1.1 PHASE0 phase
This phase is entered immediately from any phase on a power-on or enabled destructive reset event. The
reset state machine exits PHASE0 and enters PHASE1 on verification of the following:
• Power-up has completed
• Fast internal RC oscillator (16 MHz) clock is running
• All enabled destructive resets have been processed
• All processes that need to be done in PHASE0 are completed
• A minimum of 3 fast internal RC oscillator (16 MHz) clock cycles have elapsed since power-up
completion and the last enabled destructive reset event
9.4.1.2 PHASE1 phase
This phase is entered either on exit from PHASE0 or immediately from PHASE2, PHASE3, or IDLE on
a non-masked external or functional reset event if it has not been configured to trigger a short sequence.
The reset state machine exits PHASE1 and enters PHASE2 on verification of the following:
• All enabled, non-shortened functional resets have been processed
• A minimum of 10 fast internal RC oscillator (16 MHz) clock cycles have elapsed since the last
enabled external or non-shortened functional reset event