NXP Semiconductors MPC5605BK, Reference Manual

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Chapter 30 Flash Memory
MPC5606BK Microcontroller Reference Manual, Rev. 2
Freescale Semiconductor 881
sampling the read data from the flash memory array. This data is normally stored in the least-recently
updated page read buffer for bank0 in parallel with the requested data being forwarded to the AHB. For
bank1, the data is captured in the page-wide temporary holding register as the requested data is forwarded
to the AHB bus.
If the flash memory access was the direct result of an AHB transaction, the page buffer is marked as most
recently used as it is being loaded. If the flash memory access was the result of a speculative prefetch to
the next sequential line, it is first loaded into the least recently used buffer. The status of this buffer is not
changed to most recently used until a subsequent buffer hit occurs.
30.8.3 Read cycles – Buffer hit
Single cycle read responses to the AHB are possible with the platform flash memory controller when the
requested read access was previously loaded into one of the bank0 page buffers. In these buffer hit cases,
read data is returned to the AHB data phase with a zero wait-state response.
Likewise, the bank1 logic includes a single 128-bit temporary holding register and sequential accesses that
“hit” in this register are also serviced with a zero wait-state response.
30.8.4 Write cycles
Write cycles are initiated by the platform flash memory controller. The platform flash memory controller
then waits for the appropriate number of write wait-states before terminating the write operation.
30.8.5 Error termination
The first case that can cause an error response to the AHB is when an access is attempted by an AHB
master whose corresponding Read Access Control or Write Access Control settings do not allow the
access, thus causing a protection violation. In this case, the platform flash memory controller does not
initiate a flash memory array access.
The second case that can cause an error response to the AHB is when an access is performed to the flash
memory array and is terminated with a flash memory error response. See
Section 30.8.7, Flash error
response operation . This may occur for either a read or a write operation.
A third case involves an attempted read access while the flash memory array is busy doing a write
(program) or erase operation if the appropriate read-while-write control field is programmed for this
response. The 3-bit read-while-write control allows for immediate termination of an attempted read, or
various stall-while-write/erase operations are occurring.
30.8.6 Access pipelining
The platform flash memory controller does not support access pipelining since this capability is not
supported by the flash memory array. As a result, the APC (Address Pipelining Control) field must be the
same value as the RWSC (Read Wait-State Control).