NXP Semiconductors MPC5605BK, Reference Manual

Page: 120 / 964

Chapter 6 Clock Description
MPC5606BK Microcontroller Reference Manual, Rev. 2
120 Freescale Semiconductor
6.7.6 Functional description
6.7.6.1 Normal mode
In Normal Mode the FMPLL inputs are driven by the CR. This means that, when the FMPLL is in lock
state, the FMPLL output clock (PHI) is derived by the reference clock (CLKIN) through this relation:
where the value of IDF, NDIV, and ODF are set in the CR and can be derived from Table 6-10 , Table 6-11 ,
and Table 6-12 .
FM_EN Frequency Modulation Enable. The FM_EN enables the frequency modulation.
0 Frequency modulation disabled
1 Frequency modulation enabled
INC_STEP Increment step.
The INC_STEP field is the binary equivalent of the value incstep derived from following formula:
where:
md : represents the peak modulation depth in percentage (Center spread — pk-pk = ±md,
Downspread — pk-pk = –2 × md)
MDF : represents the nominal value of loop divider (CR[NDIV])
Table 6-14. FMPLL lookup table
Crystal frequency
(MHz)
FMPLL output
frequency (MHz)
CR field values
VCO frequency (MHz)
IDF ODF NDIV
8 32 0 2 32 256
64 0 2 64 512
80 0 1 40 320
16 32 1 2 32 256
64 1 2 64 512
80 1 1 40 320
40 32 4 2 32 256
64 4 2 64 512
80 3 1 32 320
Table 6-13. MR field descriptions (continued)
Field Description
incstep round
2
15
1 –
 
md

MDF

100 5

MODPERIOD

---------------------------------------------------------------
 
 
=
phi
clkin NDIV

IDF ODF

----------------------------------
=