NXP Semiconductors MPC5605BK, Reference Manual

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Chapter 26 Deserial Serial Peripheral Interface (DSPI)
MPC5606BK Microcontroller Reference Manual, Rev. 2
Freescale Semiconductor 641
See Section 26.6.3.4, Transmit First In First Out (TX FIFO) buffering mechanism , and Section 26.6.3.5,
Receive First In First Out (RX FIFO) buffering mechanism , for details on the FIFO operation. The TX
FIFO is chosen for the illustration, but the concepts carry over to the RX FIFO.
Figure 26-25 illustrates the concept of first-in and last-in FIFO entries along with the FIFO counter.
Figure 26-25. TX FIFO pointers and counter
26.7.4.1 Address calculation for the first-in entry and last-in entry in the TX FIFO
The memory address of the first-in entry in the TX FIFO is computed by the following equation:
First-in entry address = TXFIFO base + 4 (TXNXTPTR)
The memory address of the last-in entry in the TX FIFO is computed by the following equation:
Last-in entry address = TXFIFO base + 4 × [(TXCTR + TXNXTPTR – 1) modulo TXFIFO depth]
where:
TXFIFO base = base address of transmit FIFO
TXCTR = transmit FIFO counter
TXNXTPTR = transmit next pointer
TX FIFO depth = transmit FIFO depth, implementation specific
26.7.4.2 Address calculation for the first-in entry and last-in entry in the RX FIFO
The memory address of the first-in entry in the RX FIFO is computed by the following equation:
First-in entry address = RXFIFO base + 4 × (POPNXTPTR)
The memory address of the last-in entry in the RX FIFO is computed by the following equation:
Last-in entry address = RXFIFO base + 4 × [(RXCTR + POPNXTPTR – 1) modulo RXFIFO depth]
where:
RXFIFO base = base address of receive FIFO
Entry C
Entry A (first in)
– 1
Entry B
Entry D (last in)
TX FIFO base
Push TX FIFO
TX FIFO counter
Shift register SOUT
register
Transmit next
data pointer
–
–
–
–
+ 1
(TXNXTPTR)