NXP Semiconductors MPC5605BK, Reference Manual

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Chapter 8 Mode Entry Module (MC_ME)
MPC5606BK Microcontroller Reference Manual, Rev. 2
Freescale Semiconductor 157
8.3.1.7 Debug Mode Transition Status Register (ME_DMTS)
This register provides the status of different factors that influence mode transitions. It is used to give an
indication of why a mode transition indicated by ME_GS.S_MTRANS may be taking longer than
expected.
NOTE
The ME_DMTS register does not indicate whether a mode transition is
ongoing. Therefore, some ME_DMTS bits may still be asserted after the
mode transition has completed.
S_NMA Non-existing Mode Access status — This bit is set whenever the target mode requested is one of
those non existing modes determined by ME_ME register. It is cleared by writing a 1 to this bit.
0 Target mode requested is an existing mode
1 Target mode requested is a non-existing mode
S_SEA SAFE Event Active status — This bit is set whenever the device is in SAFE mode, SAFE event bit
is pending and a new mode requested other than RESET/SAFE modes. It is cleared by writing a 1 to
this bit.
0 No new mode requested other than RESET/SAFE while SAFE event is pending
1 New mode requested other than RESET/SAFE while SAFE event is pending
Address 0xC3FD_C018 Access: User read, Supervisor read/write, Test read/write
R
0 0 0 0 0 0 0 0
MPH_B
U
SY
0 0
PMC_PR
OG
CORE_DBG
0 0
SMR
W
Reset 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0
R
0 0
SYSCLK_SW
DFLASH_SC CFLASH_SC
0 0 0
W
Reset 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0
Figure 8-8. Debug Mode Transition Status Register (ME_DMTS)
Table 8-9. Invalid Mode Transition Status Register (ME_IMTS) Field Descriptions (continued)
Field Description