NXP Semiconductors MPC5605BK, Reference Manual

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Chapter 30 Flash Memory
MPC5606BK Microcontroller Reference Manual, Rev. 2
796 Freescale Semiconductor
The majority of CFlash and DFlash memory-mapped registers can be read even when the CFlash or
DFlash is in power-down or low-power mode. The exceptions are as follows:
• CFlash
— UT0[MRE, MRV, AIS, DSI0:7]
— UT1
— UT2
• DFlash
— UT0[MRE, MRV, AIS, DSI0:7]
— UT1
— UT2
The flash memory module enters the read state on reset.
The module is in the read state under two sets of conditions:
• The read state is active when the module is enabled (User mode read).
• The read state is active when the ERS and ESUS fields in the corresponding MCR
(CFLASH_MCR or DFLASH_MCR) are 1 and the PGM field is 0 (erase suspend).
Flash memory core reads return 128 bits (1 page = 2 double words).
Register reads return 32 bits (1 Word).
Flash memory core reads are done through the platform flash memory controller.
Register reads to unmapped register address space will return all 0s.
Register writes to unmapped register address space will have no effect.
Attempted array reads to invalid locations will result in indeterminate data. Invalid locations occur when
blocks that do not exist in non 2
n
array sizes are addressed.
Attempted interlock writes to invalid locations will result in an interlock occurring, but attempts to
program these blocks will not occur since they are forced to be locked. Erase will occur to selected and
unlocked blocks even if the interlock write is to an invalid location.
Simultaneous Read cycle on the Flash Matrix and Read/Write cycles on the registers are possible . On the
contrary, registers read/write accesses simultaneous to a Flash Matrix interlock write are forbidden.
30.4.6 Reset
A reset is the highest priority operation for the flash memory module and terminates all other operations.
The flash memory module uses reset to initialize register and status bits to their default reset values. If the
flash memory module is executing a program or erase operation (PGM = 1 or ERS = 1 in CFLASH_MCR
or DFLASH_MCR) and a reset is issued, the operation will be suddenly terminated and the module will
disable the high voltage logic without damage to the high voltage circuits. Reset terminates all operations
and forces the flash memory module into User mode ready to receive accesses. Reset and power-off must
not be used as a systematic way to terminate a program or erase operation.