NXP Semiconductors MPC5605BK, Reference Manual

Page: 248 / 964

Chapter 15 e200z0h Core
MPC5606BK Microcontroller Reference Manual, Rev. 2
248 Freescale Semiconductor
• Precise exception handling
• Branch processing unit
— Dedicated branch address calculation adder
— Branch acceleration using Branch Target Buffer
• Supports independent instruction and data accesses to different memory subsystems, such as
SRAM and Flash memory via independent Instruction and Data bus interface units (BIUs)
(e200z0h only).
• Load/store unit
— 1 cycle load latency
— Fully pipelined
— Big-endian support only
— Misaligned access support
— Zero load-to-use pipeline bubbles for aligned transfers
• Power management
— Low power design
— Power saving modes: nap, sleep, and wait
— Dynamic power management of execution units
• Testability
— Synthesizeable, full MuxD scan design
— ABIST/MBIST for optional memory arrays
15.4.1 Instruction unit features
The features of the e200 Instruction unit are:
• 32-bit instruction fetch path supports fetching of one 32-bit instruction per clock, or as many as
two 16-bit VLE instructions per clock
• Instruction buffer with 4 entries in e200z0h, each holding a single 32-bit instruction, or a pair of
16-bit instructions
• Dedicated PC incrementer supporting instruction prefetches
• Branch unit with dedicated branch address adder supporting single cycle of execution of certain
branches, two cycles for all others
15.4.2 Integer unit features
The e200 integer unit supports single cycle execution of most integer instructions:
• 32-bit AU for arithmetic and comparison operations
• 32-bit LU for logical operations
• 32-bit priority encoder for count leading zeros function
• 32-bit single cycle barrel shifter for shifts and rotates