NXP Semiconductors MPC5605BK, Reference Manual

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Chapter 24 LIN Controller (LINFlexD)
MPC5606BK Microcontroller Reference Manual, Rev. 2
522 Freescale Semiconductor
24.11.2 Master node, RX mode
On a master node in RX mode, the DMA interface requires a single RX channel. Each TCD controls a
single frame, except for the extended frames (multiple TCDs). The memory map associated to the TCD
chain (RAM area and LINFlexD registers) is shown in
Figure 24-45 .
Figure 24-45. TCD chain memory map (master node, RX mode)
The TCD chain of the DMA Rx channel on a master node supports Slave-to-Master reception of the data
field.
Table 24-41. TCD settings (master node, TX mode)
TCD field Value Description
CITER[14:0] 1 Single iteration for the major loop
BITER[14:0] 1 Single iteration for the major loop
NBYTES[31:0] [4 + 4] + 0/4/8 = N Data buffer is stuffed with dummy bytes if the length is
not word aligned.
BIDR + BDRL + BDRM
SADDR[31:0] RAM address
SOFF[15:0] 4 Word increment
SSIZE[2:0] 2 Word transfer
SLAST[31:0] –N
DADDR[31:0] LINCR2 address
DOFF[15:0] 4 Word increment
DSIZE[2:0] 2 Word transfer
DLAST_SGA[31:0] –N No scatter/gather processing
INT_MAJ 0/1 Interrupt disabled/enabled
D_REQ 1 Only on the last TCD of the chain.
START 0 No software request
BIDR (4 bytes)
BDRL + BDRM
(4/8 bytes)
DMA transfer
RAM area
TCD (n+2)
Linked chain
BIDR (4 bytes)
BDRL + BDRM
(8 bytes)
BDRL + BDRM
(4/8 bytes)
LINFlex2 registers
Extended
Frame (n+1)
Frame (n)
Slave

Master
1 DMA RX channel (TCD single and/or linked chain)
TCD (n+1)
TCD (n)
Extended
Frame (n+2)
BIDR (4 bytes)
BDRL + BDRM
(4/8 bytes)
BIDR (4 bytes)
BDRL + BDRM
(8 bytes)
BDRL + BDRM
(4/8 bytes)