NXP Semiconductors MPC5605BK, Reference Manual

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Chapter 34 Error Correction Status Module (ECSM)
MPC5606BK Microcontroller Reference Manual, Rev. 2
Freescale Semiconductor 933
• It provides a mechanism to allow testing of the software service routines associated with memory
error logging.
It should be noted that while the EEGR is associated with the SRAM, similar capabilities exist for the
flash, that is, the ability to program the non-volatile memory with single- or double-bit errors is supported
for the same two reasons previously identified.
For both types of memories (SRAM and flash), the intent is to generate errors during data write cycles,
such that subsequent reads of the corrupted address locations generate ECC events, either single-bit
corrections or double-bit non-correctable errors that are terminated with an error response.
Offset: 0x4A Access: Read/write
0 1 2 3 4 5 6 7 8 9 10 11 12 13 14 15
R 0 0
FRC1BI
FR11
BI
0 0
FRCN
CI
FR
1NCI
0
ERRBIT
W
Reset: 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0
Figure 34-8. ECC Error Generation Register (EEGR)
Table 34-9. EEGR field descriptions
Field Description
FRC1BI Force SRAM Continuous 1-bit Data Inversions
The assertion of this bit forces the SRAM controller to create 1-bit data inversions, as defined by the
bit position specified in ERRBIT[6:0], continuously on every write operation.
The normal ECC generation takes place in the SRAM controller, but then the polarity of the bit
position defined by ERRBIT is inverted to introduce a 1-bit ECC event in the SRAM.
After this bit has been enabled to generate another continuous 1-bit data inversion, it must be
cleared before being set again to properly re-enable the error generation logic.
This bit can only be set if the same SoC configurable input enable signal (as that used to enable
single-bit correction reporting) is asserted.
0 No SRAM continuous 1-bit data inversions are generated.
1 1-bit data inversions in the SRAM are continuously generated.
FR11BI Force SRAM One 1-bit Data Inversion
The assertion of this bit forces the SRAM controller to create one 1-bit data inversion, as defined by
the bit position specified in ERRBIT[6:0], on the first write operation after this bit is set.
The normal ECC generation takes place in the SRAM controller, but then the polarity of the bit
position defined by ERRBIT is inverted to introduce a 1-bit ECC event in the SRAM.
After this bit has been enabled to generate a single 1-bit data inversion, it must be cleared before
being set again to properly re-enable the error generation logic.
This bit can only be set if the same SoC configurable input enable signal (as that used to enable
single-bit correction reporting) is asserted.
0 No SRAM single 1-bit data inversion is generated.
1 One 1-bit data inversion in the SRAM is generated.