NXP Semiconductors MPC5605BK, Reference Manual

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Chapter 6 Clock Description
MPC5606BK Microcontroller Reference Manual, Rev. 2
Freescale Semiconductor 113
6.6 Fast internal RC oscillator (FIRC) digital interface
6.6.1 Introduction
The FIRC digital interface controls the 16 MHz fast internal RC oscillator (FIRC). It holds control and
status registers accessible for application.
6.6.2 Functional description
The FIRC provides a high frequency (f
FIRC
) clock of 16 MHz. This clock can be used to accelerate the exit
from reset and wakeup sequence from low power modes of the system. It is controlled by the MC_ME
module based on the current device mode. The clock source status is updated in ME_GS[S_RC]. Please
see
Chapter 8, Mode Entry Module (MC_ME) , for further details.
The FIRC can be further divided by a configurable division factor in the range from 1 to 32 to generate the
divided clock to match system requirements. This division factor is specified by RC_CTL[RCDIV] bits.
The FIRC output frequency can be trimmed using FIRC_CTL[FIRCTRIM]. After a power-on reset, the
FIRC is trimmed using a factory test value stored in test flash memory. However, after a power-on reset
the test flash memory value is not visible at FIRC_CTL[FIRCTRIM], and this field will show a value of 0.
Therefore, be aware that the FIRC_CTL[FIRCTRIM] field does not reflect the current trim value until you
have written to it. Pay particular attention to this feature when you initiate a read-modify-write operation
on FIRC_CTL, because a FIRCTRIM value of zero may be unintentionally written back and this may alter
the FIRC frequency. In this case, you should calibrate the FIRC using the CMU or ensure that you write
only to the upper 16 bits of this FIRC_CTL.
In this oscillator, two's complement trimming method is implemented. So the trimming code increases
from –32 to 31. As the trimming code increases, the internal time constant increases and frequency
reduces. Please refer to the device datasheet for average frequency variation of the trimming step.
Table 6-6. SIRC_CTL field descriptions
Field Description
SIRCTRIM SIRC trimming bits.
This field corresponds (via twos complement) to a trim factor of –16 to +15.
A +1 change in SIRCTRIM decreases the current frequency by

SIRCTRIM
(see the device data
sheet).
A –1 change in SIRCTRIM increases the current frequency by

SIRCTRIM
(see the device data
sheet).
SIRCDIV SIRC clock division factor.
This field specifies the SIRC oscillator output clock division factor. The output clock is divided
by the factor 1.
S_SIRC SIRC clock status.
0 SIRC is not providing a stable clock.
1 SIRC is providing a stable clock.
SIRCON_STDBY SIRC control in STANDBY mode.
0 SIRC is switched off in STANDBY mode.
1 SIRC is switched on in STANDBY mode.