NXP Semiconductors MPC5605BK, Reference Manual

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Chapter 30 Flash Memory
MPC5606BK Microcontroller Reference Manual, Rev. 2
882 Freescale Semiconductor
30.8.7 Flash error response operation
The flash memory array may signal an error response to terminate a requested access with an error. This
may occur due to an uncorrectable ECC error, or because of improper sequencing during program/erase
operations. When an error response is received, the platform flash memory controller does not update or
validate a bank0 page read buffer nor the bank1 temporary holding register. An error response may be
signaled on read or write operations. For additional information on the system registers that capture the
faulting address, attributes, data, and ECC information, see
Chapter 34, Error Correction Status Module
(ECSM) .
30.8.8 Bank0 page read buffers and prefetch operation
The logic associated with bank0 of the platform flash memory controller contains four 128-bit page read
buffers that are used to hold instructions and data read from the flash memory array. Each buffer operates
independently, and is filled using a single array access. The buffers are used for both prefetch and normal
demand fetches.
For the general case, a page buffer is written at the completion of an error-free flash memory access and
the valid bit asserted. Subsequent flash memory accesses that hit the buffer, that is, the current access
address matches the address stored in the buffer, can be serviced in 0 AHB wait-states as the stored read
data is routed from the given page buffer back to the requesting bus master.
As noted in Section 30.8.7, Flash error response operation , a page buffer is not marked as valid if the flash
memory array access terminated with any type of transfer error. However, the result is that flash memory
array accesses that are tagged with a single-bit correctable ECC event are loaded into the page buffer and
validated. For additional comments on this topic, see
Section 30.8.8.4, Buffer invalidation .
Prefetch triggering is controllable on a per-master and access-type basis. Bus masters may be enabled or
disabled from triggering prefetches, and triggering may be further restricted based on whether a read
access is for instruction or data. A read access to the platform flash memory controller may trigger a
prefetch to the next sequential page of array data on the first idle cycle following the request. The access
address is incremented to the next-higher 16-byte boundary, and a flash memory array prefetch is initiated
if the data is not already resident in a page buffer. Prefetched data is always loaded into the least recently
used buffer.
Buffers may be in one of six states, listed here in order of priority:
1. Invalid — The buffer contains no valid data.
2. Used — The buffer contains valid data that has been provided to satisfy an AHB burst type read.
3. Valid — The buffer contains valid data that has been provided to satisfy an AHB single type read.
4. Prefetched — The buffer contains valid data that has been prefetched to satisfy a potential future
AHB access.
5. Busy AHB — The buffer is currently being used to satisfy an AHB burst read.
6. Busy Fill — The buffer has been allocated to receive data from the flash memory array, and the
array access is still in progress.