NXP Semiconductors MPC5605BK, Reference Manual

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Chapter 28 Analog-to-Digital Converter (ADC)
MPC5606BK Microcontroller Reference Manual, Rev. 2
Freescale Semiconductor 763
28.4.10 Data registers
28.4.10.1 Introduction
ADC conversion results are stored in data registers. There is one register per channel.
28.4.10.2 Channel Data Register (CDR[0..95])
Table 28-39 shows the available channels.
Each data register also gives information regarding the corresponding result as described below.
For ADC_0 10-bit:
Table 28-38. PDEDR field descriptions
Field Description
PDED Delay between the power-down bit reset and the start of conversion. The delay is to allow time for the
ADC power supply to settle before commencing conversions.
The power down delay is calculated as: PDED × 1/frequency of ADC clock.
ADC Registers Description
ADC_0 CDR0[0..15] Enable bits of injected sampling for channel 0 to 15 (precision channels)
ADC_0 CDR0[32..59] Enable bits of injected sampling for channel 32 to 59 (standard channels)
ADC_0 CDR0[64..95] Enable bits of injected sampling for channel 64 to 95 (external multiplexed channels)
ADC_1 CDR1[0..15] Enable bits of injected sampling for channel 0 to 15 (precision channels)
ADC_1 CDR1[32..59] Enable bits of injected sampling for channel 32 to 39 (standard channels)
Table 28-39. CDR[0..95] register description