NXP Semiconductors MPC5605BK, Reference Manual

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Chapter 6 Clock Description
MPC5606BK Microcontroller Reference Manual, Rev. 2
Freescale Semiconductor 115
6.7 Frequency-modulated phase-locked loop (FMPLL)
6.7.1 Introduction
This section describes the features and functions of the FMPLL module implemented in the device.
6.7.2 Overview
The FMPLL enables the generation of high speed system clocks from a common 4–16 MHz input clock.
Further, the FMPLL supports programmable frequency modulation of the system clock. The FMPLL
multiplication factor and output clock divider ratio are all software configurable.
MPC5606BK has one FMPLL that can generate the system clock and takes advantage of the FM mode.
NOTE
The user must take care not to program the device with a frequency higher
than allowed (no hardware check).
The FMPLL block diagram is shown in Figure 6-6 .
Figure 6-6. FMPLL block diagram
6.7.3 Features
The FMPLL has the following major features:
• Input clock frequency 4 MHz – 16 MHz
• Voltage controlled oscillator (VCO) range from 256 MHz to 512 MHz
• Frequency divider (FD) for reduced frequency operation without forcing the FMPLL to relock
• Frequency modulated FMPLL
— Modulation enabled/disabled through software
— Triangle wave modulation
• Programmable modulation depth
— ±0.25% to ±4% deviation from center spread frequency
1
—

0.5% to +8% deviation from down spread frequency
— Programmable modulation frequency dependent on reference frequency
• Self-clocked mode (SCM) operation
1. Spread spectrum should be programmed in line with maximum datasheet frequency figures.
BUFFER
Charge
Pump
Low Pass
Filter
VCO IDF
NDIV
Loop
Frequency
Divider
ODF
PHI
FXOSC
CGM_AC0_SC
FIRC