NXP Semiconductors MPC5605BK, Reference Manual

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Chapter 22 Inter-Integrated Circuit Bus Controller Module (I
2
C)
MPC5606BK Microcontroller Reference Manual, Rev. 2
400 Freescale Semiconductor
22.3.3 I
2
C Bus Frequency Divider Register (IBFD)
Offset 0x1 Access: Read/write any time
7 6 5 4 3 2 1 0
R
IBC
W
Reset 0 0 0 0 0 0 0 0
Figure 22-3. I
2
C Bus Frequency Divider Register (IBFD)
Table 22-3. IBFD field descriptions
Field Description
IBC I-Bus Clock Rate. This field is used to prescale the clock for bit rate selection. The bit clock generator is
implemented as a prescale divider. The IBC bits are decoded to give the Tap and Prescale values as
follows:
7–6 select the prescaled shift register (see
Table 22-4 )
5–3 select the prescaler divider (see Table 22-5 )
2–0 select the shift register tap point (see Table 22-6 )
Table 22-4. I-Bus multiplier factor
IBC7
–
6 MUL
00 01
01 02
10 04
11 RESERVED
Table 22-5. I-Bus prescaler divider values
IBC5
–
3
scl2start
(clocks)
scl2stop
(clocks)
scl2tap
(clocks)
tap2tap
(clocks)
000 2 7 4 1
001 2 7 4 2
010 2 9 6 4
011 6 9 6 8
100 14 17 14 16
101 30 33 30 32
110 62 65 62 64
111 126 129 126 128