NXP Semiconductors MPC5605BK, Reference Manual

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Chapter 23 LIN Controller (LINFlex)
MPC5606BK Microcontroller Reference Manual, Rev. 2
Freescale Semiconductor 463
• If D2 > 18.75%, LHE is set.
• If D2 < 15.62%, LHE is not set.
• If 15.62% < D2 < 18.75%, LHE can be either set or reset depending on the dephasing between the
signal on LINFlex_RX pin the f
periph_set_1_clk
clock.
Note that the LINFlex does not need to check if the next edge occurs slower than expected. This is covered
by the check for deviation error on the full synch byte.
23.8.2.5 Clock gating
The LINFlex clock can be gated from the Mode Entry module (MC_ME). In LIN mode, the LINFlex
controller acknowledges a clock gating request once the frame transmission or reception is completed.
23.8.3 8-bit timeout counter
23.8.3.1 LIN timeout mode
Clearing the LTOM bit (setting its value to 0) in the LINTCSR enables the LIN timeout mode. The
LINOCR becomes read-only, and OC1 and OC2 output compare values in the LINOCR are automatically
updated by hardware.
This configuration detects header timeout, response timeout, and frame timeout.
Depending on the LIN mode (selected by the LINCR1[MME] bit), the 8-bit timeout counter will behave
differently.
LIN timeout mode must not be enabled during LIN extended frames transmission or reception (that is, if
the data field length in the BIDR is configured with a value higher than 8 data bytes).
23.8.3.1.1 LIN Master mode
The LINTOCR[RTO] field can be used to tune response timeout and frame timeout values. Header timeout
value is fixed to HTO = 28-bit time.
Field OC1 checks T
Header
and T
Response
and field OC2 checks T
Frame
(see Figure 23-32 ).
When LINFlex moves from Break delimiter state to Synch Field state (see Section 23.7.1.3, LIN status
register (LINSR) ):
• OC1 is updated with the value of OC
Header
(OC
Header
= CNT + 28),
• OC2 is updated with the value of OC
Frame
(OC
Frame
= CNT + 28 + RTO × 9 (frame timeout value
for an 8-byte frame),
• The TOCE bit is set.
On the start bit of the first response data byte (and if no error occurred during the header reception), OC1
is updated with the value of OC
Response
(OC
Response
= CNT + RTO × 9 (response timeout value for an
8-byte frame)).
On the first response byte is received, OC1 and OC2 are automatically updated to check T
Response
and
T
Frame
according to RTO (tolerance) and DFL.