NXP Semiconductors MPC5605BK, Reference Manual

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Chapter 27 Timers
MPC5606BK Microcontroller Reference Manual, Rev. 2
Freescale Semiconductor 667
EDSEL Edge Selection bit
For input modes, the EDSEL bit selects whether the internal counter is triggered by both edges of a
pulse or just by a single edge as defined by the EDPOL bit. When not shown in the mode of
operation description, this bit has no effect.
1 = Both edges triggering
0 = Single edge triggering defined by the EDPOL bit
For GPIO in mode, the EDSEL bit selects if a FLAG can be generated.
1 = No FLAG is generated
0 = A FLAG is generated as defined by the EDPOL bit
For SAOC mode, the EDSEL bit selects the behavior of the output flip-flop at each match.
1 = The output flip-flop is toggled
0 = The EDPOL value is transferred to the output flip-flop
EDPOL Edge Polarity bit
For input modes, the EDPOL bit asserts which edge triggers either the internal counter or an input
capture or a FLAG. When not shown in the mode of operation description, this bit has no effect.
1 = Trigger on a rising edge
0 = Trigger on a falling edge
For output modes, the EDPOL bit is used to select the logic level on the output pin.
1 = A match on comparator A sets the output flip-flop, while a match on comparator B clears it
0 = A match on comparator A clears the output flip-flop, while a match on comparator B sets it
MODE Mode selection
The MODE field selects the mode of operation of the Unified Channel, as shown in
Table 27-21 .
Note: If a reserved value is written to mode the results are unpredictable.
Table 27-18. UC internal prescaler clock divider
UCPRE Divide ratio
00 1
01 2
10 3
11 4
Table 27-19. UC input filter bits
IF
1
Minimum input pulse width [FLT_CLK periods]
0000 Bypassed
2
0001 02
0010 04
0100 08
1000 16
all others Reserved
Table 27-17. EMIOSC[n] field descriptions
(continued)
Field Description