NXP Semiconductors MPC5605BK, Reference Manual

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Chapter 24 LIN Controller (LINFlexD)
MPC5606BK Microcontroller Reference Manual, Rev. 2
502 Freescale Semiconductor
24.10.7 LIN timeout control status register (LINTCSR)
Offset: 0x18 Access: User read/write
0 1 2 3 4 5 6 7 8 9 10 11 12 13 14 15
R 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0
W
Reset 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0
16 17 18 19 20 21 22 23 24 25 26 27 28 29 30 31
Reset 0 0 0 0 0 0 1 0 0 0 0 0 0 0 0 0
1
These fields are writable only in Initialization mode (LINCR1[INIT] = 1).
Figure 24-24. LIN timeout control status register (LINTCSR)
Table 24-18. LINTCSR field descriptions
Name Description
LTOM LIN timeout mode
0: LIN timeout mode (header, response and frame timeout detection)
1: Output compare mode
This bit can be set/cleared in Initialization mode only.
IOT Idle on Timeout
0: LIN state machine not reset to Idle on timeout event
1: LIN state machine reset to Idle on timeout event
This bit can be set/cleared in Initialization mode only.
TOCE Timeout counter enable
0: Timeout counter disable. OCF bit in LINESR or UARTSR is not set on an output compare event.
1: Timeout counter enable. OCF bit is set if an output compare event occurs.
TOCE bit is configurable by software in Initialization mode. If LIN state is not Init and if timer is in LIN
timeout mode, then hardware takes control of TOCE bit.
CNT Counter Value
These bits indicate the LIN Timeout counter value.