NXP Semiconductors MPC5605BK, Reference Manual

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Chapter 5 Microcontroller Boot
MPC5606BK Microcontroller Reference Manual, Rev. 2
92 Freescale Semiconductor
5.2.3 FlexCAN boot
5.2.3.1 Configuration
Boot according to the FlexCAN boot mode download protocol (see Section 5.2.3.2, Protocol ) is performed
by the FlexCAN_0 module. Pins used are:
• CAN0TX mapped on PB[0]
• CAN0RX mapped on PB[1]
NOTE
When the serial download via FlexCAN is selected and the device is part of
a CAN network, the serial download may stop unexpectedly if there is any
other traffic on the network. To avoid this situation, ensure that no other
CAN device on the network is active during the serial download process.
Boot from FlexCAN uses the system clock driven by the 4–16 MHz fast external crystal oscillator.
The FlexCAN controller is configured to operate at a baud rate = system clock frequency/40 (see Table 5-6
for examples of baud rate).
It uses the standard 11-bit identifier format detailed in FlexCAN 2.0A specification.
FlexCAN controller bit timing is programmed with 10 time quanta, and the sample point is 2 time quanta
before the end, as shown in
Figure 5-11 .
Table 5-8. UART boot mode download protocol
Protocol
step
Host sent message
BAM response
message
Action
1 64-bit password
(MSB first) 64-bit password Password checked for validity and compared against
stored password.
2 32-bit store address 32-bit store address Load address is stored for future use.
3 VLE bit + 31-bit
number of bytes
(MSB first) VLE bit + 31-bit
number of bytes
(MSB first) Size of download are stored for future use.
Verify if VLE bit is set to 1
4 8 bits of raw binary
data 8 bits of raw binary
data 8-bit data are packed into a 32-bit word. This word is
saved into SRAM starting from the “Load address”.
“Load address” increments until the number of data
received and stored matches the size as specified in the
previous step.
5 None None Branch to downloaded code