Chapter 26 Deserial Serial Peripheral Interface (DSPI)
MPC5606BK Microcontroller Reference Manual, Rev. 2
Freescale Semiconductor
627
26.6.5
Transfer formats
The SPI serial communication is controlled by the serial communications clock (SCK_
x
) signal and the
CS
x
signals. The SCK_
x
signal provided by the master device synchronizes shifting and sampling of the
data by the SIN_
x
and SOUT_
x
pins. The CS
x
signals serve as enable signals for the slave devices.
When the DSPI is the bus master, the CPOL and CPHA bits in the DSPI clock and transfer attributes
registers (DSPI
x
_CTAR
n
) select the polarity and phase of the serial clock, SCK_
x
. The polarity bit selects
the idle state of the SCK_
x
. The clock phase bit selects if the data on SOUT_
x
is valid before or on the first
SCK_
x
edge.
When the DSPI is the bus slave, CPOL and CPHA bits in the DSPI
x
_CTAR0 (SPI slave mode) select the
polarity and phase of the serial clock. Even though the bus slave does not control the SCK signal, clock
polarity, clock phase and number of bits to transfer must be identical for the master device and the slave
device to ensure proper transmission.
The DSPI supports four different transfer formats:
•
Classic SPI with CPHA = 0
•
Classic SPI with CPHA = 1
•
Modified transfer format with CPHA = 0
•
Modified transfer format with CPHA = 1
A modified transfer format is supported to allow for high-speed communication with peripherals that
require longer setup times. The DSPI can sample the incoming data later than halfway through the cycle
to give the peripheral more setup time. The MTFE bit in the DSPI
x
_MCR selects between classic SPI
format and modified transfer format. The classic SPI formats are described in
Section 26.6.5.2, Classic SPI transfer format (CPHA = 1)
transfer formats are described in
Section 26.6.5.3, Modified SPI transfer format (MTFE = 1, CPHA = 0)
,
and
Section 26.6.5.4, Modified SPI transfer format (MTFE = 1, CPHA = 1)
In the SPI configuration, the DSPI provides the option of keeping the CS signals asserted between frames.
See
Section 26.6.5.5, Continuous selection format
for details.
Table 26-30. Peripheral chip select strobe negate computation example
PASC
Prescaler
f
SYS
Delay after transfer
0b11
7
64 MHz
109.4 ns
Summary of Contents for MPC5605BK
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Page 103: ...MPC5606BK Microcontroller Reference Manual Rev 2 Freescale Semiconductor 103 Clocks and power...
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