NXP Semiconductors MPC5605BK, Reference Manual

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Chapter 32 Register Protection
MPC5606BK Microcontroller Reference Manual, Rev. 2
Freescale Semiconductor 901
32.6.2.1 Change lock settings directly via area #4
Memory area #4 contains the lock bits. They can be modified by writing to them. Each SLBR n .SLB m bit
has a mask bit SLBR n .WE m, which protects it from being modified. This masking makes
clear-modify-write operations unnecessary.
Figure 32-5 shows two modification examples. In the left example there is a write access to the SLBR n
register specifying a mask value that allows modification of all SLBR n .SLB m bits. The example on the
right specifies a mask that only allows modification of the bits SLBR n .SLB[3:1].
Figure 32-5. Change lock settings directly via Area #4
Figure 32-5 shows four registers that can be protected 8-bit wise. In Figure 32-6 registers with 16-bit
protection and in Figure 32-7 registers with 32-bit protection are shown:
Figure 32-6. Change lock settings for 16-bit protected addresses
On the right side of Figure 32-6 it is shown that the data written to SLBR n .SLB[0] is automatically written
to SLBR n .SLB[1] also. This is done as the address reflected by SLBR n .SLB[0] is protected 16-bit wise.
Note that in this case the write enable SLBR n .WE[0] must be set while SLBR n .WE[1] does not matter. As
the enable bits SLBR n .WE[3:2] are cleared the lock bits SLBR n .SLB[3:2] remain unchanged.
In the example on the left side of Figure 32-6 the data written to SLBR n .SLB[0] is mirrored to
SLBR n .SLB[1] and the data written to SLBR n .SLB[2] is mirrored to SLBR n .SLB[3] as for both registers
the write enables are set.
1
SLB3 SLB2 SLB1 SLB0
SLBR n .WE[3:0]
SLBR n .SLB[3:0]
SLB3 SLB2 SLB1 SLB0
SLBR n .SLB[3:0]
change allowed
to SLB3
write data
to SLB2 to SLB1 to SLB0
1 1 1 1 SLBR n .WE[3:0]
to SLB3
write data
to SLB2 to SLB1 to SLB0
1 1 0
change allowed
SLB0 SLB1 SLB2 SLB3
SLBR
update lock bits
1 SLBR n .WE[3:0]
to SLB0
write data
to SLB1 to SLB2 to SLB3
X 1 X
SLB0 SLB1 SLB2 SLB3
SLBR
update lock bits
1 SLBR n .WE[3:0]
to SLB0
write data
to SLB1 to SLB2 to SLB3
X 0 0