NXP Semiconductors MPC5605BK, Reference Manual

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Chapter 21 Memory Protection Unit (MPU)
MPC5606BK Microcontroller Reference Manual, Rev. 2
Freescale Semiconductor 377
• Support for three XBAR slave port connections: flash controller, system SRAM controller and
peripherals bus:
— MPU hardware continuously monitors every XBAR slave port access using the
preprogrammed memory region descriptors.
— An access protection error is detected if a memory reference does not hit in any memory region
or the reference is flagged as illegal in all memory regions where it does hit. In the event of an
access error, the XBAR reference is terminated with an error response and the MPU inhibits
the bus cycle being sent to the targeted slave device.
— 64-bit error registers, one for each XBAR slave port, capture the last faulting address,
attributes, and detail information.
• Global MPU enable/disable control bit provides a mechanism to easily load region descriptors
during system startup or allow complete access rights during debug with the module disabled.
21.3 Modes of operation
The MPU module does not support any special modes of operation. As a memory-mapped device located
on the platform’s high-speed system bus, it responds based strictly on the memory addresses of the
connected system buses. The peripheral bus is used to access the MPU’s programming model and the
memory protection functions are evaluated on a reference-by-reference basis using the addresses from the
XBAR system bus port(s).
Power dissipation is minimized when the MPU’s global enable/disable bit is cleared
(MPU_CESR[VLD] = 0).
21.4 External signal description
The MPU module does not include any external interface. The MPU’s internal interfaces include a
peripheral bus connection for accessing the programming model and multiple connections to the address
phase signals of the platform crossbar’s slave AHB ports. From a platform topology viewpoint, the MPU
module appears to be directly connected downstream from the crossbar switch with interfaces to the
XBAR slave ports.
21.5 Memory map and register description
The MPU module provides an IPS programming model mapped to an SPP-standard on-platform 16 KB
space. The programming model is partitioned into three groups: control/status registers, the data structure
containing the region descriptors and the alternate view of the region descriptor access control values.
The programming model can only be referenced using 32-bit (word) accesses. Attempted references using
different access sizes, to undefined (reserved) addresses, or with a non-supported access type (for example,
a write to a read-only register or a read of a write-only register) generate an IPS error termination.
Finally, the programming model allocates space for an MPU definition with 8 region descriptors and as
many as three XBAR slave ports, like flash controller, system SRAM controller and peripheral bus.