NXP Semiconductors MPC5605BK, Reference Manual

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Chapter 21 Memory Protection Unit (MPU)
MPC5606BK Microcontroller Reference Manual, Rev. 2
Freescale Semiconductor 385
M6WE Bus master 6 write enable
If set, this flag allows bus master 6 to perform write operations. If cleared, any attempted write by bus
master 6 terminates with an access error and the write is not performed.
M5RE Bus master 5 read enable
If set, this flag allows bus master 5 to perform read operations. If cleared, any attempted read by bus
master 5 terminates with an access error and the read is not performed.
M5WE Bus master 5 write enable
If set, this flag allows bus master 5 to perform write operations. If cleared, any attempted write by bus
master 5 terminates with an access error and the write is not performed.
M4RE Bus master 4 read enable
If set, this flag allows bus master 4 to perform read operations. If cleared, any attempted read by bus
master 4 terminates with an access error and the read is not performed.
M4WE Bus master 4 write enable
If set, this flag allows bus master 4 to perform write operations. If cleared, any attempted write by bus
master 4 terminates with an access error and the write is not performed.
M3PE Bus master 3 process identifier enable
If set, this flag specifies that the process identifier and mask (defined in MPU_RGDn.Word3) are to be
included in the region hit evaluation. If cleared, then the region hit evaluation does not include the
process identifier.
M3SM Bus master 3 supervisor mode access control
This field defines the access controls for bus master 3 when operating in supervisor mode. The M3SM
field is defined as:
00 r, w, x = read, write and execute allowed
01 r, –, x = read and execute allowed, but no write
10 r, w, – = read and write allowed, but no execute
11 Same access controls as that defined by M3UM for user mode
M3UM Bus master 3 user mode access control
This field defines the access controls for bus master 3 when operating in user mode. The M3UM field
consists of three independent bits, enabling read, write and execute permissions: {r,w,x}. If set, the bit
allows the given access type to occur; if cleared, an attempted access of that mode may be terminated
with an access error (if not allowed by any other descriptor) and the access not performed.
M2PE Bus master 2 process identifier enable
If set, this flag specifies that the process identifier and mask (defined in MPU_RGDn.Word3) are to be
included in the region hit evaluation. If cleared, then the region hit evaluation does not include the
process identifier.
M2SM Bus master 2 supervisor mode access control
This field defines the access controls for bus master 2 when operating in supervisor mode. The M2SM
field is defined as:
00 r, w, = read and write allowed
01 r = read allowed, but no write
10 r, w = read and write allowed
11 Same access controls as that defined by M2UM for user mode
M2UM Bus master 2 user mode access control
This field defines the access controls for bus master 2 when operating in user mode. The M2UM field
consists of two independent bits, enabling read and write permissions: {r,w}. If set, the bit allows the
given access type to occur; if cleared, an attempted access of that mode may be terminated with an
access error (if not allowed by any other descriptor) and the access not performed.
Table 21-8. MPU_RGD n .Word2 field descriptions (continued)
Field Description