NXP Semiconductors MPC5605BK, Reference Manual

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Chapter 16 Enhanced Direct Memory Access (eDMA)
MPC5606BK Microcontroller Reference Manual, Rev. 2
Freescale Semiconductor 271
16.3.2.17 Transfer Control Descriptor (TCD)
Each channel requires a 32-byte transfer control descriptor for defining the desired data movement
operation. The channel descriptors are stored in the local memory in sequential order: channel 0, channel
1,... channel 15. The definitions of the TCD are presented as eight 32-bit values.
Table 16-18 is a field list
of the basic TCD structure.
Figure 16-18 and Table 16-19 define the fields of the TCD n structure.
Table 16-17. EDMA_CPRn field descriptions
Field Description
ECP Enable Channel Preemption
0 Channel n cannot be suspended by a higher priority channel’s service request.
1 Channel n can be temporarily suspended by the service request of a higher priority
channel.
DPA Disable Preempt Ability
0 Channel n can suspend a lower priority channel.
1 Channel n cannot suspend any channel, regardless of channel priority.
CHPRI[0:3] Channel n Arbitration Priority
Channel priority when fixed-priority arbitration is enabled.
Table 16-18. TCDn 32-bit memory structure
eDMA offset
TCDn field
(32 × n)+0x0000 Source address (saddr)
(32 × n)+0x0004 Transfer attributes Signed source address offset (soff)
(32 × n)+0x0008 Inner minor byte count (nbytes)
(32 × n)+0x000C Last source address adjustment (slast)
(32 × n)+0x0010 Destination address (daddr)
(32 × n)+0x0014 Current major iteration count (citer) Signed destination address offset (doff)
0x1000 (32 × n) 0x0018 Last destination address adjustment / scatter-gather address (dlast_sga)
(32 × n)+0x001C Beginning major iteration count (biter) Channel control/status