NXP Semiconductors MPC5605BK, Reference Manual

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Chapter 35 IEEE 1149.1 Test Access Port Controller (JTAGC)
MPC5606BK Microcontroller Reference Manual, Rev. 2
950 Freescale Semiconductor
The TAP controller is a synchronous state machine that interprets the sequence of logical values on the
TMS pin.
Figure 35-5 shows the machine’s states. The value shown next to each state is the value of the
TMS signal sampled on the rising edge of the TCK signal.
As Figure 35-5 shows, holding TMS at logic 1 while clocking TCK through a sufficient number of rising
edges also causes the state machine to enter the test-logic-reset state.
Figure 35-5. IEEE 1149.1-2001 TAP controller finite state machine
Test logic
reset
Run-test/idle
Select-DR-scan
Select-IR-scan
Capture-DR
Capture-IR
Shift-DR Shift-IR
Exit1-DR Exit1-IR
Pause-DR
Pause-IR
Exit2-DR
Exit2-IR
Update-DR
Update-IR
1
0
1
1
1
0 0
0
0
1
1
0
0
1
1
1
1
0
0
0
0
1 1
1
1
0
0
1
1
0
0
0
NOTE: The value shown adjacent to each state transition in this figure represents the value of TMS at the time
of a rising edge of TCK.