NXP Semiconductors MPC5605BK, Reference Manual

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Chapter 7 Clock Generation Module (MC_CGM)
MPC5606BK Microcontroller Reference Manual, Rev. 2
Freescale Semiconductor 141
7.5.3.2 Auxiliary Clock 0 Select Control Register (CGM_AC0_SC)
This register is used to select the current clock source for the FMPLL reference clock.
DIV1 Divider 1 Division Value — The resultant peripheral set 2 clock will have a period DIV1 + 1 times that of
the system clock. If the DE1 is set to 0 (Divider 1 is disabled), any write access to the DIV1 field is ignored
and the peripheral set 2 clock remains disabled.
DE2 Divider 2 Enable
0 Disable system clock divider 2
1 Enable system clock divider 2
DIV2 Divider 2 Division Value — The resultant peripheral set 3 clock will have a period DIV2 + 1 times that of
the system clock. If the DE2 is set to 0 (Divider 2 is disabled), any write access to the DIV2 field is ignored
and the peripheral set 3 clock remains disabled.
Address 0xC3FE_0380 Access: User read, Supervisor read/write, Test read/write
0 1 2 3 4 5 6 7 8 9 10 11 12 13 14 15
R 0 0 0 0
SELCTL
0 0 0 0 0 0 0 0
W
Reset 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0
16 17 18 19 20 21 22 23 24 25 26 27 28 29 30 31
R 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0
W
Reset 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0
Figure 7-6. Auxiliary Clock 0 Select Control Register (CGM_AC0_SC)
Table 7-7. Auxiliary Clock 0 Select Control Register (CGM_AC0_SC) Field Descriptions
Field Description
SELCTL Auxiliary Clock 0 Source Selection Control — This value selects the current source for auxiliary clock
0.
0000 FXOSC
0001 FIRC
0010 reserved
0011 reserved
0100 reserved
0101 reserved
0110 reserved
0111 reserved
1000 reserved
1001 reserved
1010 reserved
1011 reserved
1100 reserved
1101 reserved
1110 reserved
1111 reserved
Table 7-6. System Clock Divider Configuration Registers (CGM_SC_DC0…2) Field Descriptions (continued)
Field Description