NXP Semiconductors MPC5605BK, Reference Manual

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Chapter 2 Introduction
MPC5606BK Microcontroller Reference Manual, Rev. 2
Freescale Semiconductor 35
2.4 Feature details
2.4.1 e200z0h core processor
The e200z0h core includes the following features:
• High performance, e200z0h core processor for managing peripherals and interrupts
• Single issue 4-stage pipelined in-order execution, 32-bit Power Architecture CPU
• Variable length encoding (VLE), allowing mixed 16-bit and 32-bit instructions
— Results in efficient code size footprint
— Minimizes impact on performance
• Branch processing acceleration using lookahead instruction buffer
• Load/store unit
— 1-cycle load latency
— Misaligned access support
— No load-to-use pipeline bubbles
• 32-bit general purpose registers (GPRs)
• Separate instruction bus and load/store bus Harvard architecture
• Hardware vectored interrupt support
• Multi-cycle divide word (divw) and load multiple word (lmw) store multiple word (smw) multiple
class instructions, can be interrupted to prevent increases in interrupt latency
2.4.2 Crossbar switch (XBAR)
The following summarizes the MPC5606BK’s implementation of the crossbar switch:
• Three master ports:
— CPU instruction bus
— CPU load/store bus
— eDMA
• Multiple bus slaves to enable access to flash memory, SRAM, and peripherals
• Crossbar supports as many as two consecutive transfers at any one time
• 32-bit internal address bus, 32-bit internal data bus
• Fixed priority arbitration based on port master
2.4.3 Interrupt Controller (INTC)
The MPC5606BK implements an interrupt controller that features the following:
• Unique 9-bit vector for each of the 231 separate interrupt sources
• Eight software triggerable interrupt sources