NXP Semiconductors MPC5605BK, Reference Manual

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Chapter 1 Preface
MPC5606BK Microcontroller Reference Manual, Rev. 2
Freescale Semiconductor 25
1.4 Register description conventions
The register information for MPC5606BK is presented in:
• Memory maps containing:
— An offset from the module’s base address
— The name and acronym/abbreviation of each register
— The page number on which each register is described
• Register figures
• Field-description tables
• Associated text
The register figures show the field structure using the conventions in Figure 1-1 .
Figure 1-1. Register figure conventions
The numbering of register bits and fields on MPC5606BK is as follows:
32 Register Protection Certain registers in each peripheral can be protected
from further writes using the register protection
mechanism detailed in this section. Registers can
either be configured to be unlocked via a soft lock bit
or locked unit the next reset. Integrity
33 Software Watchdog Timer
(SWT) The SWT offers a selection of configurable modes that
can be used to monitor the operation of the
microcontroller and /or reset the device or trigger an
interrupt if the SWT is not correctly serviced. The SWT
is enabled out of reset.
34 Error Correction Status Module
(ECSM) Provides information about the last reset, general
device information, system fault information and
detailed ECC error information.
35 IEEE 1149.1 Test Access Port
Controller (JTAGC) Used for boundary scan as well as device debug. Debug
Table 1-1. Guide to this reference manual (continued)
Chapter
Description Functional group
# Title
R 0 1
W
R FIELD1 FIELD2
W
R
FIELD
W
Reserved bits Read-only fields Read/write fields
R FIELD
W w1c
“Write 1 to clear” field
(field will always read 0)
R 0 0 0
W FIELD1 FIELD2
Write-only fields