NXP Semiconductors MPC5605BK, Reference Manual

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Chapter 25 FlexCAN
MPC5606BK Microcontroller Reference Manual, Rev. 2
592 Freescale Semiconductor
— Determine the internal arbitration mode (LBUF bit)
• Initialize the Message Buffers
— The Control and Status word of all Message Buffers must be initialized
— If FIFO was enabled, the 8-entry ID table must be initialized
— Other entries in each Message Buffer should be initialized as required
• Initialize the Rx Individual Mask registers
• Set required interrupt mask bits in the IMASK registers (for all MB interrupts), in CTRL (for Bus
Off and Error interrupts), and in MCR for Wake-Up interrupt
• Negate the HALT bit in MCR
Starting with the last event, FlexCAN attempts to synchronize to the CAN bus.
25.6.2 FlexCAN addressing and RAM size configurations
There are three RAM configurations that can be implemented within the FlexCAN module. The possible
configurations are:
• For 16 MBs: 288 bytes for MB memory and 64 bytes for Individual Mask registers
• For 32 MBs: 544 bytes for MB memory and 128 bytes for Individual Mask registers
• For 64 MBs: 1056 bytes for MB memory and 256 bytes for Individual Mask registers
In each configuration the user can program the maximum number of MBs that will take part in the
matching and arbitration processes using the MAXMB field in MCR. For 16 MB configuration, MAXMB
can be any number between 0–15. For 32 MB configuration, MAXMB can be any number between 0–31.
For 64 MB configuration, MAXMB can be any number between 0–63.