NXP Semiconductors MPC5605BK, Reference Manual

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Chapter 28 Analog-to-Digital Converter (ADC)
MPC5606BK Microcontroller Reference Manual, Rev. 2
Freescale Semiconductor 739
28.4.2.2 Main Status Register (MSR)
The Main Status Register (MSR) provides status bits for the ADC.
ACKO Auto-clock-off enable
If set, this bit enables the Auto clock off feature.
0 Auto clock off disabled
1 Auto clock off enabled
PWDN Power-down enable
When this bit is set, the analog module is requested to enter Power Down mode. When ADC
status is PWDN, resetting this bit starts ADC transition to IDLE mode.
0 ADC is in normal mode
1 ADC has been requested to power down
Address: Base + 0x0004 Access: User read-only
0 1 2 3 4 5 6 7 8 9 10 11 12 13 14 15
R
0 0 0 0 0 0 0
NS
T
A
R
T
J
ABOR
T
0 0
JST
A
R
T
0 0 0
CTUST
A
R
T
W
Reset 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0
16 17 18 19 20 21 22 23 24 25 26 27 28 29 30 31
R CHADDR 0 0 0 ACK0 0 0 ADCSTATUS
W
Reset 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 1
Figure 28-10. Main Status Register (MSR)
Table 28-12. MSR field descriptions
Field Description
NSTART This status bit is used to signal that a Normal conversion is ongoing.
JABORT This status bit is used to signal that an Injected conversion has been aborted. This bit is reset when
a new injected conversion starts.
JSTART This status bit is used to signal that an Injected conversion is ongoing.
CTUSTART This status bit is used to signal that a CTU conversion is ongoing.
CHADDR Current conversion channel address
This status field indicates current conversion channel address.
ACKO Auto-clock-off enable
This status bit is used to signal if the Auto-clock-off feature is on.
Table 28-11. MCR field descriptions (continued)
Field Description