NXP Semiconductors MPC5605BK, Reference Manual

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Chapter 24 LIN Controller (LINFlexD)
MPC5606BK Microcontroller Reference Manual, Rev. 2
532 Freescale Semiconductor
24.11.6 UART node, RX mode
In UART RX mode, the DMA interface requires a DMA RX channel. A single TCD can control the
reception of an entire Rx buffer. The memory map associated with the TCD chain (RAM area and
LINFlexD registers) is shown in
Figure 24-53 .
Figure 24-53. TCD chain memory map (UART node, RX mode)
Table 24-47. TCD settings (UART node, TX mode)
TCD Field
Value
Description
8-bit data 16-bit data
CITER[14:0] M Multiple iterations for the major loop
BITER[14:0] M Multiple iterations for the major loop
NBYTES[31:0] 1 2 Minor loop transfer = 1 or 2 bytes
SADDR[31:0] RAM address
SOFF[15:0] 1 2 Byte/half-word increment
SSIZE[2:0] 0 1 Byte/half-word transfer
SLAST[31:0] –M –M × 2
DADDR[31:0] BDRL address DADDR = BDRL + 0x3 for byte transfer
DADDR = BDRL + 0x2 for half-word
transfer
DOFF[15:0] 0 No increment (FIFO)
DSIZE[2:0] 0 1 Byte/Half-word transfer
DLAST_SGA[31:0] 0 No scatter/gather processing
INT_MAJ 0/1 Interrupt disabled/enabled
D_REQ 1 Only on the last TCD of the chain.
START 0 No software request
Buffer (n+1)
Buffer (n)
DMA transfer (8/16-bit data format)
RAM area LINFlex2 registers
1 DMA RX channel (TCD single and/or linked chain)
BDRM
(4 bytes FIFO mode)
BDRM
(2 half-words FIFO mode)
BDRM
(4 bytes FIFO mode)
BDRM
(2 half-words FIFO mode)
TCD (n+1)
TCD (n)
BDRM
(M bytes)
BDRM
(M half-words)
BDRM
(M bytes)
BDRM
(M half-words)