Chapter 30 Flash Memory
MPC5606BK Microcontroller Reference Manual, Rev. 2
Freescale Semiconductor
821
30.5.1.8
CFlash User Test 0 register (CFLASH_UT0)
The User Test Registers provide the user with the ability to test features on the flash memory module. The
User Test 0 Register allows to control the way in which the flash memory content check is done.
Bits MRE, MRV, AIS, EIE, and DSI[7:0] of the User Test 0 Register are not accessible whenever
CFLASH_MCR[DONE] or UT0[AID] are low: reading returns indeterminate data while writing has no
effect.
Offset: 0x0003C
Access: Read/write
0
1
2
3
4
5
6
7
8
9
10
11
12
13
14
15
R UTE
0
0
0
0
0
0
0
DSI
W w1c
Reset
0
0
0
0
0
0
0
0
0
0
0
0
0
0
0
0
16
17
18
19
20
21
22
23
24
25
26
27
28
29
30
31
R
0
0
0
0
0
0
0
0
0
X
MRE MRV
EIE
AIS
AIE
AID
W
Reset
0
0
0
0
0
0
0
0
0
0
0
0
0
0
0
1
Figure 30-13. CFlash User Test 0 register (CFLASH_UT0)
Table 30-24. CFLASH_UT0 field descriptions
Field
Description
UTE
User Test Enable
This status bit gives indication when User Test is enabled. All bits in CFLASH_UT0-2 and
CFLASH_UMISR0-4 are locked when this bit is 0.
The method to set this bit is to provide a password, and if the password matches, the UTE
bit is set to reflect the status of enabled, and is enabled until it is cleared by a register write.
For UTE the password 0xF9F99999 must be written to the CFLASH_UT0 register.
DSI
Data Syndrome Input
These bits represent the input of Syndrome bits of ECC logic used in the ECC logic check.
Bits DSI[7:0] correspond to the 8 syndrome bits on a double word.
These bits are not accessible whenever CFLASH_MCR[DONE] or CFLASH_UT0[AID] are
low: reading returns indeterminate data while writing has no effect.
0 The syndrome bit is forced at 0.
1 The syndrome bit is forced at 1.
X
Reserved
This bit can be written and its value can be read back, but there is no function associated.
This bit is not accessible whenever CFLASH_MCR[DONE] or CFLASH_UT0[AID] are low:
reading returns indeterminate data while writing has no effect.
Summary of Contents for MPC5605BK
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