NXP Semiconductors MPC5605BK, Reference Manual

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Chapter 11 Voltage Regulators and Power Supplies
MPC5606BK Microcontroller Reference Manual, Rev. 2
208 Freescale Semiconductor
11.1.3 Ultra low power regulator (ULPREG)
The ULPREG generates power for the standby domain as well as a part of the main domain and might or
might not see the external capacitance. The control circuit of ULPREG can be used to disable the ultra low
power regulator by software: This action is managed by MC_ME.
11.1.4 LVDs and POR
There are three kinds of LVD available:
1. LVD_MAIN for the 3.3 V–5 V input supply with thresholds at approximately 3 V level
1
2. LVD_MAIN5 for the 3.3 V–5 V input supply with threshold at approximately 4.5 V level
1
3. LVD_DIG for the 1.2 V output voltage
The LVD_MAIN and LVD_MAIN5 sense the 3.3 V–5 V power supply for CORE, shared with IO ring
supply and indicate when the 3.3 V–5 V supply is stabilized.
Two LVD_DIGs are provided in the design. One LVD_DIG is placed in the high power domain and senses
the HPREG/LPREG output notifying that the 1.2 V output is stable. The other LVD_DIG is placed in the
standby domain and senses the standby 1.2 V supply level notifying that the 1.2 V output is stable. The
reference voltage used for all LVDs is generated by the low power reference generator and is trimmed for
LVD_DIG, using the bits LP[4:7]. Therefore, during the pre-trimming period, LVD_DIG exhibits higher
thresholds, whereas during post trimming, the thresholds come in the desired range. Power-down pins are
provided for LVDs. When LVDs are power-down, their outputs are pulled high.
POR is required to initialize the device during supply rise. POR works only on the rising edge of the main
supply. To ensure its functioning during the following rising edge of the supply, it is reset by the output of
the LVD_MAIN block when main supply reaches below the lower voltage threshold of the LVD_MAIN.
POR is asserted on power-up when Vdd supply is above V
PORUP
min (refer to data sheet for details). It
will be released only after Vdd supply is above V
PORH
(refer to data sheet for details). Vdd above V
PORH
ensures power management module including internal LVDs modules are fully functional.
11.1.5 VREG digital interface
The voltage regulator digital interface provides the temporization delay at initial power-up and at exit from
low-power modes. A signal, indicating that Ultra Low Power domain is powered, is used at power-up to
release reset to temporization counter. At exit from low-power modes, the power-down for high power
regulator request signal is monitored by the digital interface and used to release reset to the temporization
counter. In both cases, on completion of the delay counter, a end-of-count signal is released, it is gated with
an other signal indicating main domain voltage fine in order to release the VREGOK signal. This is used
by MC_RGM to release the reset to the device. It manages other specific requirements, like the transition
between high power/low power mode to ultra low power mode avoiding a voltage drop below the
permissible threshold limit of 1.08 V.
The VREG digital interface also holds control register to mask 5 V LVD status coming from the voltage
regulator at the power-up.
1. See section “Voltage monitor electrical characteristics” of the data sheet for detailed information about this voltage value.