NXP Semiconductors MPC5605BK, Reference Manual

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Chapter 28 Analog-to-Digital Converter (ADC)
MPC5606BK Microcontroller Reference Manual, Rev. 2
Freescale Semiconductor 721
The conversion times are programmed via the bit fields of the CTR. Bit fields INPLATCH, INPCMP, and
INPSAMP are used to define the total conversion duration (T
conv
) and in particular the partition between
sampling phase duration (T
sample
) and total evaluation phase duration (T
eval
).
28.3.3.1 ADC_0
Figure 28-4 represents the sampling and conversion sequence.
Figure 28-4. Sampling and conversion timings
The sampling phase duration is:
where ndelay is equal to 0.5 if INPSAMP is less than or equal to 06h, otherwise it is 1. INPSAMP must
be greater than or equal to 3 (hardware requirement).
The total evaluation phase duration is:
INPCMP must be greater than or equal to 1 and INPLATCH must be less than INCMP (hardware
requirements).
The total conversion duration is (not including external multiplexing):
The timings refer to the unit T
ck
, where f
ck
= (1/2 × ADC peripheral set clock).
0.5 cycles
2.5 cycles
Sampling phase Successive approximation / evaluation phase
10 cycles
Latching phase:
The capacitors field input
switch is opened
Note: Operating conditions — INPLATCH = 0, INPSAMP = 3, INPCMP = 1 and Fadc clk = 20 MHz
End of conversion
T
sample
INPSAMP ndelay –
 
T
ck

=
INPSAMP 3

T
eval
10 T
biteval

10 INPCMP T
ck
   
= =
INPCMP 1
  
and INPLATCH INPCMP
  
T
conv
T
sample
T
eval
ndelay T
ck
  
+ + =