NXP Semiconductors MPC5605BK, Reference Manual

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Chapter 21 Memory Protection Unit (MPU)
MPC5606BK Microcontroller Reference Manual, Rev. 2
376 Freescale Semiconductor
Figure 21-1. MPU block diagram
21.2 Features
The Memory Protection Unit implements a two-dimensional hardware array of memory region descriptors
and the crossbar slave XBAR ports to continuously monitor the legality of every memory reference
generated by each bus master in the system. The feature set includes:
• Support for eight memory region descriptors, each 128 bits in size
— Specification of start and end addresses provide granularity for region sizes from 32 bytes to
4 GB
— Access control definitions: two bus masters (processor cores) support the traditional {read,
write, execute} permissions with independent definitions for supervisor and user mode
accesses
— Automatic hardware maintenance of the region descriptor valid bit removes issues associated
with maintaining a coherent image of the descriptor
— Alternate memory view of the access control word for each descriptor provides an efficient
mechanism to dynamically alter only the access rights of a descriptor
— For overlapping region descriptors, priority is given to permission granting over access
denying as this approach provides more flexibility to system software. See Section 21.6.2,
Putting it all together and AHB error terminations, for details and Section 21.8, Application
information, for an example.
PFlash
PRAM
PBRIDGE0
Core (z0hn2p)
XBAR MPU
s0
s2
s7
m0
m1
Platform
m2
eDMA