NXP Semiconductors MPC5605BK, Reference Manual

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Chapter 5 Microcontroller Boot
MPC5606BK Microcontroller Reference Manual, Rev. 2
Freescale Semiconductor 91
Since the ECC on the SRAM has not been initialized (except for the bytes of data that have just been
downloaded), an additional dummy word of 0x0000_0000 is written at the end of the downloaded data
block to avoid any ECC errors during core prefetch.
5.2.1.6 Execute code
The BAM code waits for the last data byte to be received. If the operating mode is censored with a private
password, then the BAM reads the SSCM status register to determine whether the serial password matched
the private password. If there was a password match, then the BAM code restores the initial configuration
and transfers execution to the downloaded code start address in SRAM. If the passwords did not match,
the BAM code forces a static mode entry.
NOTE
The watchdog is disabled at the start of BAM code execution. In the case of
an unexpected issue during BAM code execution, the microcontroller may
be stalled and an external reset required to recover the microcontroller.
5.2.2 LINFlex (RS232) boot
5.2.2.1 Configuration
Boot according to the LINFlex boot mode download protocol (see Section 5.2.2.2, Protocol ) is performed
by the LINFlex_0 module in UART (RS232) mode. Pins used are:
• LIN0TX mapped on PB[2]
• LIN0RX mapped on PB[3]
Boot from LINFlex uses the system clock driven by the 4–16 MHz external crystal oscillator (FXOSC).
The LINFlex controller is configured to operate at a baud rate = system clock frequency/833, using an 8-bit
data frame without parity bit and 1 stop bit.
Figure 5-10. LINFlex bit timing in UART mode
5.2.2.2 Protocol
Table 5-8 summarizes the protocol and BAM action during this boot mode.
D1 D2 D3 D4 D5 D6 D7 D0
Byte field
Start
bit
Stop
bit