NXP Semiconductors MPC5605BK, Reference Manual

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Chapter 30 Flash Memory
MPC5606BK Microcontroller Reference Manual, Rev. 2
838 Freescale Semiconductor
A number of DFLASH_MCR bits are protected against write when another bit, or set of bits, is in a specific
state. These write locks are covered on a bit by bit basis in the preceding description, but those locks do
not consider the effects of trying to write two or more bits simultaneously.
The flash memory module does not allow the user to write bits simultaneously, which would put the device
into an illegal state. This is implemented through a priority mechanism among the bits. The bit changing
priorities are detailed in the
Table 30-41 .
If the user attempts to write two or more DFLASH_MCR bits simultaneously then only the bit with the
lowest priority level is written.
110 64 KB
111 Reserved
Table 30-39. Low address space configuration
LAS Low address space sectorization
000 Reserved
001 Reserved
010 32 KB + 2 × 16 KB + 2 × 32 KB + 128 KB
011 Reserved
100 Reserved
101 Reserved
110 4 × 16 KB
111 Reserved
Table 30-40. Mid address space configuration
MAS Mid address space sectorization
0 2 × 128KB
1 Reserved
Table 30-41. DFLASH_MCR bits set/clear priority levels
Priority level DFLASH_MCR bits
1 ERS
2 PGM
3 EHV
4 ESUS
Table 30-38. Array space size (continued)
SIZE Array space size