NXP Semiconductors MPC5605BK, Reference Manual

Page: 380 / 964

Chapter 21 Memory Protection Unit (MPU)
MPC5606BK Microcontroller Reference Manual, Rev. 2
380 Freescale Semiconductor
21.5.2.2 MPU Error Address Register, Slave Port n (MPU_EAR n )
When the MPU detects an access error on slave port n , the 32-bit reference address is captured in this
read-only register and the corresponding bit in the MPU_CESR[SPERR] field set. Additional information
about the faulting access is captured in the corresponding MPU_EDR
n register at the same time. Note this
register and the corresponding MPU_EDR n register contain the most recent access error; there are no
hardware interlocks with the MPU_CESR[SPERR] field as the error registers are always loaded upon the
occurrence of each protection violation.
VLD Valid
This bit provides a global enable/disable for the MPU.
0 The MPU is disabled.
1 The MPU is enabled.
While the MPU is disabled, all accesses from all bus masters are allowed.
Table 21-3. SPERR implementation
SPERR bit Corresponding port
SPERR[0] Flash memory controller slave port
SPERR[1] System RAM controller slave port
SPERR[2] IPS peripheral bus slave port
Offsets: 0x010–0x020 (3 registers) Access: Read
0 1 2 3 4 5 6 7 8 9 10 11 12 13 14 15
R EADDR [31:16]
W
Reset – – – – – – – – – – – – – – – –
16 17 18 19 20 21 22 23 24 25 26 27 28 29 30 31
R EADDR [15:0]
W
Reset – – – – – – – – – – – – – – – –
Figure 21-3. MPU Error Address Register, Slave Port n (MPU_EARn)
Table 21-4. MPU_EAR n field descriptions
Field Description
EADDR Error Address
This field is the reference address from slave port n that generated the access error.
Table 21-2. MPU_CESR field descriptions (continued)
Field Description