NXP Semiconductors MPC5605BK, Reference Manual

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Chapter 27 Timers
MPC5606BK Microcontroller Reference Manual, Rev. 2
706 Freescale Semiconductor
NOTE
Register Address = Base A Address Offset, where the Base Address
is defined at the MCU level and the Address Offset is defined at the module
level.
NOTE
Reserved registers will read as 0, writes will have no effect.
27.5.4.2 PIT Module Control Register (PITMCR)
This register controls whether the timer clocks should be enabled and whether the timers should run in
debug mode.
27.5.4.3 Timer Load Value Register (LDVAL)
This register selects the timeout period for the timer interrupts.
Offset: 0x000 Access: Read/Write
0 1 2 3 4 5 6 7 8 9 10 11 12 13 14 15
R 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0
W
Reset 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0
16 17 18 19 20 21 22 23 24 25 26 27 28 29 30 31
R 0 0 0 0 0 0 0 0 0 0 0 0 0 0
MDIS FRZ
W
Reset 0 0 0 0 0 0 0 0 0 0 0 0 0 0 1 0
Figure 27-57. PIT Module Control Register (PITMCR)
Table 27-25. PITMCR field descriptions
Field Description
MDIS Module Disable
This is used to disable the module clock. This bit should be enabled before any other setup is done.
0 Clock for PIT timers is enabled
1 Clock for PIT timers is disabled (default)
FRZ Freeze
Allows the timers to be stopped when the device enters debug mode.
0 = Timers continue to run in debug mode.
1 = Timers are stopped in debug mode.